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#define CSL_CPGMAC_SL_MACCONTROL_CMD_IDLE_EN (1 << 11u) |
Enable idle mode
#define CSL_CPGMAC_SL_MACCONTROL_EXT_EN (1 << 18u) |
Enable external control mode
#define CSL_CPGMAC_SL_MACCONTROL_FULLDUPLEX_EN (1 << 0u) |
MAC control register configuration definitions.
Enable full duplex mode
#define CSL_CPGMAC_SL_MACCONTROL_GIG_EN (1 << 7u) |
Enable Gigabit mode
#define CSL_CPGMAC_SL_MACCONTROL_GIG_FORCE_EN (1 << 17u) |
Enable forced Gigabit mode
#define CSL_CPGMAC_SL_MACCONTROL_GMII_EN (1 << 5u) |
Enable GMII
#define CSL_CPGMAC_SL_MACCONTROL_IFCTL_A_EN (1 << 15u) |
Set IFCTL_A bit to 1
#define CSL_CPGMAC_SL_MACCONTROL_IFCTL_B_EN (1 << 16u) |
Set IFCTL_B bit to 1
#define CSL_CPGMAC_SL_MACCONTROL_LOOPBACK_EN (1 << 1u) |
Enable loopback mode
#define CSL_CPGMAC_SL_MACCONTROL_RX_CEF_EN (1 << 22u) |
Enable Rx copy error frames mode
#define CSL_CPGMAC_SL_MACCONTROL_RX_CMF_EN (1 << 24u) |
Enable Rx copy MAC control frames mode
#define CSL_CPGMAC_SL_MACCONTROL_RX_CSF_EN (1 << 23u) |
Enable Rx copy short frames mode
#define CSL_CPGMAC_SL_MACCONTROL_RX_FLOW_EN (1 << 3u) |
Enable Rx flow control mode
#define CSL_CPGMAC_SL_MACCONTROL_TX_FLOW_EN (1 << 4u) |
Enable Tx flow control mode
#define CSL_CPGMAC_SL_MACCONTROL_TX_PACE_EN (1 << 6u) |
Enable Tx pacing
#define CSL_CPGMAC_SL_MACCONTROL_TX_SHORT_GAP_EN (1 << 10u) |
Enable Tx short gap
#define hCpgmacSlRegs ((CSL_Cpgmac_slPortRegs *) (CSL_PA_SS_CFG_REGS + 0x00090900)) |
Pointer to the EMAC overlay registers.
Constants for passing parameters to the functions.