EDMA3

Modules

 EDMA3 Symbols Defined
 EDMA3 Data Structures
 EDMA3 Functions
 EDMA3 Enumerated Data Types

Detailed Description

Introduction

Overview

This page describes the Functions, Data Structures, Enumerations and Macros within EDMA module.

The EDMA controller handles all data transfers between the level-two (L2) cache/memory controller and the device peripherals.These data transfers include cache servicing, noncacheable memory accesses, user-programmed data transfers, and host accesses. The EDMA supports up to 64-event channels and 8 QDMA channels. The EDMA consists of a scalable Parameter RAM (PaRAM) that supports flexible ping-pong, circular buffering, channel-chaining, auto-reloading, and memory protection. The EDMA allows movement of data to/from any addressable memory spaces, including internal memory (L2 SRAM), peripherals, and external memory.

References

  1. CSL 3.x Technical Requirements Specifications Version 0.5, dated May 14th, 2003
  2. EDMA Channel Controller Specification (Revision 3.0.2)
  3. EDMA Transfer Controller Specification (Revision 3.0.1)

Assumptions

The abbreviations EDMA, edma and Edma have been used throughout this document to refer to Enhanced Direct Memory Access.


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