Output Enanble Delay
[TSIP Enumerated Data Types]

TSIP Output Enanble Delay. More...

Enumerations

enum  CSL_TsipDlyCtrl { CSL_TSIP_DLY_CTRL_DISABLE = 0, CSL_TSIP_DLY_CTRL_ENABLE = 1 }

Detailed Description

TSIP Output Enanble Delay.

Use this symbol to represent Output Enanble Delay This symbol is used on both RCV and XMT


Enumeration Type Documentation

Enumerator:
CSL_TSIP_DLY_CTRL_DISABLE 

No Added Delay

CSL_TSIP_DLY_CTRL_ENABLE 

Active High


Copyright 2012, Texas Instruments Incorporated