pcieSerdesCfg0Reg_s Struct Reference
[PCIE LLD Application Register Definitions]

Specification of the SERDES config 0 Register. More...

#include <pcie.h>

Data Fields

uint32_t raw
uint8_t txLoopback
 [rw] Enable Tx loopback. Set both bits high to enable.
uint8_t txMsync
 [rw] Master mode for synchronization.
uint8_t txCm
 [rw] Enable common mode adjustment.
uint8_t txInvpair
 [rw] Invert Tx pair polarity.
uint8_t rxLoopback
 [rw] Enable Rx loopback. Set both bits to high to enable loopback.
uint8_t rxEnoc
 [rw] Enable Rx offset compensation.
uint8_t rxEq
 [rw] Enable Rx adaptive equalization.
uint8_t rxCdr
 [rw] Enable Rx clock data recovery.
uint8_t rxLos
 [rw] Enable Rx loss of signal detection.
uint8_t rxAlign
 [rw] Enable Rx symbol alignment.
uint8_t rxInvpair
 [rw] Invert Rx pair polarity.

Detailed Description

Specification of the SERDES config 0 Register.


Field Documentation

[ro] Raw image of register on read; actual value on write

[rw] Enable Rx symbol alignment.

Field size: 2 bits

[rw] Enable Rx clock data recovery.

Field size: 3 bits

[rw] Enable Rx offset compensation.

Field size: 1 bit

[rw] Enable Rx adaptive equalization.

Field size: 4 bits

[rw] Invert Rx pair polarity.

Field size: 1 bit

[rw] Enable Rx loopback. Set both bits to high to enable loopback.

Field size: 2 bits

[rw] Enable Rx loss of signal detection.

Field size: 3 bits

[rw] Enable common mode adjustment.

Field size: 1 bit

[rw] Invert Tx pair polarity.

Field size: 1 bit

[rw] Enable Tx loopback. Set both bits high to enable.

Field size: 2 bits

[rw] Master mode for synchronization.

Field size: 1 bit


The documentation for this struct was generated from the following file:

Copyright 2012, Texas Instruments Incorporated