pcieRstCmdReg_s Struct Reference
[PCIE LLD Application Register Definitions]

Specification of the Reset Command Register. More...

#include <pcie.h>

Data Fields

uint32_t raw
 [ro] Raw image of register on read; actual value on write
uint8_t flush
 [ro] Bridge flush status
uint8_t initRst
 [w1] Write 1 to initiate a downstream hot reset sequence on downstream.

Detailed Description

Specification of the Reset Command Register.


Field Documentation

[ro] Bridge flush status

Used to ensure no pending transactions prior to issuing warm reset. 0 = No transaction is pending. 1 = There are transactions pending.

Field size: 1 bit

[w1] Write 1 to initiate a downstream hot reset sequence on downstream.

Field size: 1 bit


The documentation for this struct was generated from the following file:

Copyright 2012, Texas Instruments Incorporated