PCIE LLD Application Register Definitions
[PCIE LLD Register Definitions]

Data Structures

struct  pciePidReg_s
 Specification of the PCIe Peripheral ID Register. More...
struct  pcieCmdStatusReg_s
 Specification of the Command Status Register. More...
struct  pcieCfgTransReg_s
 Specification of the Configuration Transaction Setup Register. More...
struct  pcieIoBaseReg_s
 Specification of the IO TLP Base Register. More...
struct  pcieTlpCfgReg_s
 Specification of the TLP configuration Register. More...
struct  pcieRstCmdReg_s
 Specification of the Reset Command Register. More...
struct  pciePmCmdReg_s
 Specification of the Power Management Command Register. More...
struct  pciePmCfgReg_s
 Specification of the Power Management Configuration Register. More...
struct  pcieActStatusReg_s
 Specification of the Activity Status Register. More...
struct  pcieObSizeReg_s
 Specification of the Outbound Size Register. More...
struct  pcieDiagCtrlReg_s
 Specification of the Diagnostic Control register. More...
struct  pcieEndianReg_s
 Specification of the Endian Register. More...
struct  pciePriorityReg_s
 Specification of the Transaction Priority Register. More...
struct  pcieIrqEOIReg_s
 Specification of the End of Interrupt Register. More...
struct  pcieMsiIrqReg_s
 Specification of the MSI Interrupt IRQ Register. More...
struct  pcieEpIrqSetReg_s
 Specification of the Endpoint Interrupt Request Set Register. More...
struct  pcieEpIrqClrReg_s
 Specification of the Endpoint Interrupt Request Clear Register. More...
struct  pcieEpIrqStatusReg_s
 Specification of the Endpoint Interrupt status Register. More...
struct  pcieGenPurposeReg_s
 Specification of a General Purpose register. More...
struct  pcieMsiIrqStatusRawReg_s
 Specification of the MSI Raw Interrupt Status Register Register. More...
struct  pcieMsiIrqStatusReg_s
 Specification of the MSI Interrupt Enabled Status Register Register. More...
struct  pcieMsiIrqEnableSetReg_s
 Specification of the MSI Interrupt Enable Set Register. More...
struct  pcieMsiIrqEnableClrReg_s
 Specification of the MSI Interrupt Enable Clear Register. More...
struct  pcieLegacyIrqStatusRawReg_s
 Specification of the Legacy Raw Interrupt Status Register. More...
struct  pcieLegacyIrqStatusReg_s
 Specification of the Legacy Interrupt Enabled Status Register. More...
struct  pcieLegacyIrqEnableSetReg_s
 Specification of the Legacy Interrupt Enable Set Register. More...
struct  pcieLegacyIrqEnableClrReg_s
 Specification of the Legacy Interrupt Enable Clear Register. More...
struct  pcieErrIrqStatusRawReg_s
 Specification of the Raw ERR Interrupt Status Register. More...
struct  pcieErrIrqStatusReg_s
 Specification of the ERR Interrupt Enabled Status Register. More...
struct  pcieErrIrqEnableSetReg_s
 Specification of the ERR Interrupt Enable Set Register. More...
struct  pcieErrIrqEnableClrReg_s
 Specification of the ERR Interrupt Enable Clear Register. More...
struct  pciePmRstIrqStatusRawReg_s
 Specification of the Raw Power Management and Reset Interrupt Status Register. More...
struct  pciePmRstIrqStatusReg_s
 Specification of the Power Management and Reset Interrupt Enabled Status Register. More...
struct  pciePmRstIrqEnableSetReg_s
 Specification of the Power Management and Reset Interrupt Enable Set Register. More...
struct  pciePmRstIrqEnableClrReg_s
 Specification of the Power Management and Reset Interrupt Enable Clear Register. More...
struct  pcieObOffsetLoReg_s
 Specification of the Outbound Translation Region Offset Low and Index Register. More...
struct  pcieObOffsetHiReg_s
 Specification of the Outbound Translation Region Offset High Register. More...
struct  pcieIbBarReg_s
 Specification of the Inbound Translation BAR Match Register. More...
struct  pcieIbStartLoReg_s
 Specification of the Inbound Translation Start Address Low Register. More...
struct  pcieIbStartHiReg_s
 Specification of the Inbound Translation Start Address High Register. More...
struct  pcieIbOffsetReg_s
 Specification of the Inbound Translation Address Offset Register. More...
struct  pciePcsCfg0Reg_s
 Specification of the PCS Configuration 0 Register. More...
struct  pciePcsCfg1Reg_s
 Specification of the PCS Configuration 1 Register. More...
struct  pciePcsStatusReg_s
 Specification of the PCS Status Register. More...
struct  pcieSerdesCfg0Reg_s
 Specification of the SERDES config 0 Register. More...
struct  pcieSerdesCfg1Reg_s
 Specification of the SERDES config 1 Register. More...



typedef struct pciePidReg_s pciePidReg_t
 Specification of the PCIe Peripheral ID Register.



typedef struct pcieCmdStatusReg_s pcieCmdStatusReg_t
 Specification of the Command Status Register.



typedef struct pcieCfgTransReg_s pcieCfgTransReg_t
 Specification of the Configuration Transaction Setup Register.



typedef struct pcieIoBaseReg_s pcieIoBaseReg_t
 Specification of the IO TLP Base Register.



typedef struct pcieTlpCfgReg_s pcieTlpCfgReg_t
 Specification of the TLP configuration Register.



typedef struct pcieRstCmdReg_s pcieRstCmdReg_t
 Specification of the Reset Command Register.



typedef struct pciePmCmdReg_s pciePmCmdReg_t
 Specification of the Power Management Command Register.



typedef struct pciePmCfgReg_s pciePmCfgReg_t
 Specification of the Power Management Configuration Register.



typedef struct pcieActStatusReg_s pcieActStatusReg_t
 Specification of the Activity Status Register.



typedef struct pcieObSizeReg_s pcieObSizeReg_t
 Specification of the Outbound Size Register.



typedef struct pcieDiagCtrlReg_s pcieDiagCtrlReg_t
 Specification of the Diagnostic Control register.



typedef struct pcieEndianReg_s pcieEndianReg_t
 Specification of the Endian Register.



typedef struct pciePriorityReg_s pciePriorityReg_t
 Specification of the Transaction Priority Register.



typedef struct pcieIrqEOIReg_s pcieIrqEOIReg_t
 Specification of the End of Interrupt Register.



typedef struct pcieMsiIrqReg_s pcieMsiIrqReg_t
 Specification of the MSI Interrupt IRQ Register.



typedef struct pcieEpIrqSetReg_s pcieEpIrqSetReg_t
 Specification of the Endpoint Interrupt Request Set Register.



typedef struct pcieEpIrqClrReg_s pcieEpIrqClrReg_t
 Specification of the Endpoint Interrupt Request Clear Register.



typedef struct pcieEpIrqStatusReg_s pcieEpIrqStatusReg_t
 Specification of the Endpoint Interrupt status Register.



typedef struct pcieGenPurposeReg_s pcieGenPurposeReg_t
 Specification of a General Purpose register.



typedef struct
pcieMsiIrqStatusRawReg_s 
pcieMsiIrqStatusRawReg_t
 Specification of the MSI Raw Interrupt Status Register Register.



typedef struct
pcieMsiIrqStatusReg_s 
pcieMsiIrqStatusReg_t
 Specification of the MSI Interrupt Enabled Status Register Register.



typedef struct
pcieMsiIrqEnableSetReg_s 
pcieMsiIrqEnableSetReg_t
 Specification of the MSI Interrupt Enable Set Register.



typedef struct
pcieMsiIrqEnableClrReg_s 
pcieMsiIrqEnableClrReg_t
 Specification of the MSI Interrupt Enable Clear Register.



typedef struct
pcieLegacyIrqStatusRawReg_s 
pcieLegacyIrqStatusRawReg_t
 Specification of the Legacy Raw Interrupt Status Register.



typedef struct
pcieLegacyIrqStatusReg_s 
pcieLegacyIrqStatusReg_t
 Specification of the Legacy Interrupt Enabled Status Register.



typedef struct
pcieLegacyIrqEnableSetReg_s 
pcieLegacyIrqEnableSetReg_t
 Specification of the Legacy Interrupt Enable Set Register.



typedef struct
pcieLegacyIrqEnableClrReg_s 
pcieLegacyIrqEnableClrReg_t
 Specification of the Legacy Interrupt Enable Clear Register.



typedef struct
pcieErrIrqStatusRawReg_s 
pcieErrIrqStatusRawReg_t
 Specification of the Raw ERR Interrupt Status Register.



typedef struct
pcieErrIrqStatusReg_s 
pcieErrIrqStatusReg_t
 Specification of the ERR Interrupt Enabled Status Register.



typedef struct
pcieErrIrqEnableSetReg_s 
pcieErrIrqEnableSetReg_t
 Specification of the ERR Interrupt Enable Set Register.



typedef struct
pcieErrIrqEnableClrReg_s 
pcieErrIrqEnableClrReg_t
 Specification of the ERR Interrupt Enable Clear Register.



typedef struct
pciePmRstIrqStatusRawReg_s 
pciePmRstIrqStatusRawReg_t
 Specification of the Raw Power Management and Reset Interrupt Status Register.



typedef struct
pciePmRstIrqStatusReg_s 
pciePmRstIrqStatusReg_t
 Specification of the Power Management and Reset Interrupt Enabled Status Register.



typedef struct
pciePmRstIrqEnableSetReg_s 
pciePmRstIrqEnableSetReg_t
 Specification of the Power Management and Reset Interrupt Enable Set Register.



typedef struct
pciePmRstIrqEnableClrReg_s 
pciePmRstIrqEnableClrReg_t
 Specification of the Power Management and Reset Interrupt Enable Clear Register.



typedef struct pcieObOffsetLoReg_s pcieObOffsetLoReg_t
 Specification of the Outbound Translation Region Offset Low and Index Register.



typedef struct pcieObOffsetHiReg_s pcieObOffsetHiReg_t
 Specification of the Outbound Translation Region Offset High Register.



typedef struct pcieIbBarReg_s pcieIbBarReg_t
 Specification of the Inbound Translation BAR Match Register.



typedef struct pcieIbStartLoReg_s pcieIbStartLoReg_t
 Specification of the Inbound Translation Start Address Low Register.



typedef struct pcieIbStartHiReg_s pcieIbStartHiReg_t
 Specification of the Inbound Translation Start Address High Register.



typedef struct pcieIbOffsetReg_s pcieIbOffsetReg_t
 Specification of the Inbound Translation Address Offset Register.



typedef struct pciePcsCfg0Reg_s pciePcsCfg0Reg_t
 Specification of the PCS Configuration 0 Register.



typedef struct pciePcsCfg1Reg_s pciePcsCfg1Reg_t
 Specification of the PCS Configuration 1 Register.



typedef struct pciePcsStatusReg_s pciePcsStatusReg_t
 Specification of the PCS Status Register.



typedef struct pcieSerdesCfg0Reg_s pcieSerdesCfg0Reg_t
 Specification of the SERDES config 0 Register.



typedef struct pcieSerdesCfg1Reg_s pcieSerdesCfg1Reg_t
 Specification of the SERDES config 1 Register.

Typedef Documentation

Specification of the Command Status Register.

This Register is used to enable address translation, link training and writing to BAR mask registers.

Specification of the Inbound Translation BAR Match Register.

There are multiple instances (0-3) of this register.

Specification of the Inbound Translation Address Offset Register.

There are multiple instances (0-3) of this register.

Specification of the Inbound Translation Start Address High Register.

There are multiple instances (0-3) of this register.

Specification of the Inbound Translation Start Address Low Register.

There are multiple instances (0-3) of this register.

Specification of the Legacy Interrupt Enable Clear Register.

There are multiple instances (0-7) of this register.

Specification of the Legacy Interrupt Enable Set Register.

There are multiple instances (0-7) of this register.

Specification of the Legacy Raw Interrupt Status Register.

There are multiple instances A-D (0-3) of this register.

Specification of the Legacy Interrupt Enabled Status Register.

There are multiple instances (0-7) of this register.

Specification of the MSI Interrupt Enable Clear Register.

There are multiple instances (0-7) of this register.

Specification of the MSI Interrupt Enable Set Register.

There are multiple instances (0-7) of this register.

Specification of the MSI Raw Interrupt Status Register Register.

There are multiple instances (0-7) of this register.

Specification of the MSI Interrupt Enabled Status Register Register.

There are multiple instances (0-7) of this register.

Specification of the Outbound Translation Region Offset High Register.

There is one register per translation region (0-7)

Specification of the Outbound Translation Region Offset Low and Index Register.

There is one register per translation region (0-7)

typedef struct pciePidReg_s pciePidReg_t

Specification of the PCIe Peripheral ID Register.

This Register contains the major and minor revisions for the PCIe module.


Copyright 2012, Texas Instruments Incorporated