Data Structures

Here are the data structures with brief descriptions:
pcieAccrReg_sSpecification of the Advanced capabilities and control Register
pcieAckFreqReg_sSpecification of the Ack Frequency register
pcieActStatusReg_sSpecification of the Activity Status Register
pcieBar32bitReg_sSpecification of the Base Address Register (BAR)
pcieBarCfg_sSpecification of pcieBarCfg
pcieBarReg_sSpecification of the Base Address Register (BAR)
pcieBistReg_sSpecification of the BIST Header Register
pcieCapPtrReg_sSpecification of the Capability Pointer Register
pcieCfgTransReg_sSpecification of the Configuration Transaction Setup Register
pcieCmdStatusReg_sSpecification of the Command Status Register
pcieCorErrMaskReg_sSpecification of the Correctable Error Mask register
pcieCorErrReg_sSpecification of the Correctable Error Status register
pcieDebug0Reg_sSpecification of the Debug0 Register
pcieDebug1Reg_sSpecification of the Debug 1 Register
pcieDevCap2Reg_sSpecification of the Device Capabilities 2 Register
pcieDeviceCapReg_sSpecification of the Device Capabilities Register
pcieDevStatCtrl2Reg_sSpecification of the Device Status and Control Register 2
pcieDevStatCtrlReg_sSpecification of the Device Status and Control Register
pcieDiagCtrlReg_sSpecification of the Diagnostic Control register
pcieEndianReg_sSpecification of the Endian Register
pcieEpIrqClrReg_sSpecification of the Endpoint Interrupt Request Clear Register
pcieEpIrqSetReg_sSpecification of the Endpoint Interrupt Request Set Register
pcieEpIrqStatusReg_sSpecification of the Endpoint Interrupt status Register
pcieErrIrqEnableClrReg_sSpecification of the ERR Interrupt Enable Clear Register
pcieErrIrqEnableSetReg_sSpecification of the ERR Interrupt Enable Set Register
pcieErrIrqStatusRawReg_sSpecification of the Raw ERR Interrupt Status Register
pcieErrIrqStatusReg_sSpecification of the ERR Interrupt Enabled Status Register
pcieErrSrcIDReg_sSpecification of the Error Source Identification register
pcieExpRomReg_sSpecification of the Expansion ROM Register
pcieExtCapReg_sSpecification of the Extended Capabilities Header register
pcieFltMask2Reg_sSpecification of the Filter Mask 2 register
pcieGen2Reg_sSpecification of the Gen2 Register
pcieGenPurposeReg_sSpecification of a General Purpose register
pcieHdrLogReg_sSpecification of the Header Log registers
pcieIbBarReg_sSpecification of the Inbound Translation BAR Match Register
pcieIbOffsetReg_sSpecification of the Inbound Translation Address Offset Register
pcieIbStartHiReg_sSpecification of the Inbound Translation Start Address High Register
pcieIbStartLoReg_sSpecification of the Inbound Translation Start Address Low Register
pcieIbTransCfg_sSpecification of pcieIbTransCfg
pcieIntPinReg_sSpecification of the Interrupt Pin Register
pcieIoBaseReg_sSpecification of the IO TLP Base Register
pcieIrqEOIReg_sSpecification of the End of Interrupt Register
pcieLaneSkewReg_sSpecification of the Lane Skew register
pcieLegacyIrqEnableClrReg_sSpecification of the Legacy Interrupt Enable Clear Register
pcieLegacyIrqEnableSetReg_sSpecification of the Legacy Interrupt Enable Set Register
pcieLegacyIrqStatusRawReg_sSpecification of the Legacy Raw Interrupt Status Register
pcieLegacyIrqStatusReg_sSpecification of the Legacy Interrupt Enabled Status Register
pcieLinkCapReg_sSpecification of the Link Capabilities Register
pcieLinkCtrl2Reg_sSpecification of the Link Control 2 Register
pcieLinkStatCtrlReg_sSpecification of the Link Status and Control Register
pcieLnkCtrlReg_sSpecification of the Port Link Control Register
pcieMsiCapReg_sSpecification of the MSI capabilities Register
pcieMsiDataReg_sSpecification of the MSI Data Register
pcieMsiIrqEnableClrReg_sSpecification of the MSI Interrupt Enable Clear Register
pcieMsiIrqEnableSetReg_sSpecification of the MSI Interrupt Enable Set Register
pcieMsiIrqReg_sSpecification of the MSI Interrupt IRQ Register
pcieMsiIrqStatusRawReg_sSpecification of the MSI Raw Interrupt Status Register Register
pcieMsiIrqStatusReg_sSpecification of the MSI Interrupt Enabled Status Register Register
pcieMsiLo32Reg_sSpecification of the MSI lower 32 bits Register
pcieMsiUp32Reg_sSpecification of the MSI upper 32 bits Register
pcieObOffsetHiReg_sSpecification of the Outbound Translation Region Offset High Register
pcieObOffsetLoReg_sSpecification of the Outbound Translation Region Offset Low and Index Register
pcieObSizeReg_sSpecification of the Outbound Size Register
pciePciesCapReg_sSpecification of the PCI Express Capabilities Register
pciePcsCfg0Reg_sSpecification of the PCS Configuration 0 Register
pciePcsCfg1Reg_sSpecification of the PCS Configuration 1 Register
pciePcsStatusReg_sSpecification of the PCS Status Register
pciePidReg_sSpecification of the PCIe Peripheral ID Register
pciePlAckTimerReg_sSpecification of the Ack Latency Time and Replay Timer register
pciePlForceLinkReg_sSpecification of the Port Force Link register
pciePlOMsgReg_sSpecification of the Other Message register
pciePMCapCtlStatReg_sSpecification of the Power Management Capabilities Control and Status Register
pciePMCapReg_sSpecification of the Power Management Capability Register
pciePmCfgReg_sSpecification of the Power Management Configuration Register
pciePmCmdReg_sSpecification of the Power Management Command Register
pciePmRstIrqEnableClrReg_sSpecification of the Power Management and Reset Interrupt Enable Clear Register
pciePmRstIrqEnableSetReg_sSpecification of the Power Management and Reset Interrupt Enable Set Register
pciePmRstIrqStatusRawReg_sSpecification of the Raw Power Management and Reset Interrupt Status Register
pciePmRstIrqStatusReg_sSpecification of the Power Management and Reset Interrupt Enabled Status Register
pciePrefBaseUpperReg_sSpecification of the Prefetchable Memory Base Upper Register
pciePrefLimitUpperReg_sSpecification of the Prefetchable Memory Limit Upper Register
pciePrefMemReg_sSpecification of the Prefetchable Memory Limit and Base Register
pciePriorityReg_sSpecification of the Transaction Priority Register
pcieRegisters_sSpecification all registers
pcieRevIdReg_sSpecification of the Class code and revision ID Register
pcieRootCtrlCapReg_sSpecification of the Root Control and Capabilities Register
pcieRootErrCmdReg_sSpecification of the Root Error Command register
pcieRootErrStReg_sSpecification of the Root Error Status register
pcieRootStatusReg_sSpecification of the Root Status and Control register
pcieRstCmdReg_sSpecification of the Reset Command Register
pcieSerdesCfg0Reg_sSpecification of the SERDES config 0 Register
pcieSerdesCfg1Reg_sSpecification of the SERDES config 1 Register
pcieSlotCapReg_sSpecification of the Slot Capabilities register
pcieSlotStatCtrlReg_sSpecification of the Slot Status and Control register
pcieStatusCmdReg_sSpecification of the Status Command Register
pcieSubIdReg_sSpecification of the Subsystem Vendor ID Register
pcieSymNumReg_sSpecification of the Symbol Number register
pcieSymTimerFltMaskReg_sSpecification of the Symbol Timer and Filter Mask register
pcieTlpCfgReg_sSpecification of the TLP configuration Register
pcieType0Bar32bitIdx_spcieBar32bitReg_s register plus an index (End Point BAR)
pcieType0BarIdx_spcieBarReg_s register plus an index (End Point BAR)
pcieType1Bar32bitIdx_spcieBar32bitReg_s register plus an index (Root Complex BAR)
pcieType1BarIdx_spcieBarReg_s register plus an index (Root Complex BAR)
pcieType1BistHeaderReg_sSpecification of the BIST, Header Type, Latency Time and Cache Line Size Regiser
pcieType1BridgeIntReg_sSpecification of the Bridge Control and Interrupt Register
pcieType1BusNumReg_sSpecification of the Latency Timer and Bus Number Register
pcieType1CapPtrReg_sSpecification of the Capabilities Pointer Register
pcieType1ExpnsnRomReg_sSpecification of the Expansion ROM Base Address Register
pcieType1IOSpaceReg_sSpecification of the IO Base and Limit Upper 16 bits Register
pcieType1MemspaceReg_sSpecification of the Memory Limit and Base Register
pcieType1SecStatReg_sSpecification of the Secondary Status and IO Base/Limit Register
pcieUncErrMaskReg_sSpecification of the Uncorrectable Error Mask register
pcieUncErrReg_sSpecification of the Uncorrectable Error Status register
pcieUncErrSvrtyReg_sSpecification of the Uncorrectable Error Severity register
pcieVndDevIdReg_sSpecification of the Vendor Device ID Register

Copyright 2012, Texas Instruments Incorporated