HYPLNK LLD Register Definitions
[HYPLNK LLD Module API]

Data Structures

struct  hyplnkRevReg_s
 Specification of the HyperLink Revision Register. More...
struct  hyplnkControlReg_s
 Specification of the HyperLink Control Register. More...
struct  hyplnkStatusReg_s
 Specification of the HyperLink Status Register. More...
struct  hyplnkIntPriVecReg_s
 Specification of the Hyperlink Interrupt Priority Vector Status/Clear Register. More...
struct  hyplnkIntStatusClrReg_s
 Specification of the Hyperlink Interrupt Status/Clear Register. More...
struct  hyplnkIntPendSetReg_s
 Specification of the Hyperlink Interrupt Pending/Set Register. More...
struct  hyplnkGenSoftIntReg_s
 Specification of the Hyperlink Generate Soft Interrupt Value Register. More...
struct  hyplnkTXAddrOvlyReg_s
 Specification of the Tx Address Overlay Control Register. More...
struct  hyplnkRXAddrSelReg_s
 Specification of the Rx Address Selector Control Register. More...
struct  hyplnkRXPrivIDIdxReg_s
 Specification of the Rx Address PrivID Index Register. More...
struct  hyplnkRXPrivIDValReg_s
 Specification of the Rx Address PrivID Value Register. More...
struct  hyplnkRXSegIdxReg_s
 Specification of the Rx Address Segment Index Register. More...
struct  hyplnkRXSegValReg_s
 Specification of the Rx Address Segment Value Register. More...
struct  hyplnkChipVerReg_s
 Specification of the Chip Version Register. More...
struct  hyplnkLanePwrMgmtReg_s
 Specification of the Lane Power Management Control Register. More...
struct  hyplnkECCErrorsReg_s
 Specification of the ECC Error Counters Register. More...
struct  hyplnkLinkStatusReg_s
 Specification of the Link Status Register. More...
struct  hyplnkIntCtrlIdxReg_s
 Specification of the Interupt Control Index Register. More...
struct  hyplnkIntCtrlValReg_s
 Specification of the Interrupt Control Value Register. More...
struct  hyplnkIntPtrIdxReg_s
 Specification of the Interupt Control Index Register. More...
struct  hyplnkIntPtrValReg_s
 Specification of the Interrupt Control Value Register. More...
struct  hyplnkSERDESControl1Reg_s
 Specification of the SerDes Control And Status 1 Register. More...
struct  hyplnkSERDESControl2Reg_s
 Specification of the SerDes Control And Status 2 Register. More...
struct  hyplnkSERDESControl3Reg_s
 Specification of the SerDes Control And Status 3 Register. More...
struct  hyplnkSERDESControl4Reg_s
 Specification of the SerDes Control And Status 4 Register. More...



typedef struct hyplnkRevReg_s hyplnkRevReg_t
 Specification of the HyperLink Revision Register.



typedef struct hyplnkControlReg_s hyplnkControlReg_t
 Specification of the HyperLink Control Register.



typedef struct hyplnkStatusReg_s hyplnkStatusReg_t
 Specification of the HyperLink Status Register.



typedef struct hyplnkIntPriVecReg_s hyplnkIntPriVecReg_t
 Specification of the Hyperlink Interrupt Priority Vector Status/Clear Register.



typedef struct
hyplnkIntStatusClrReg_s 
hyplnkIntStatusClrReg_t
 Specification of the Hyperlink Interrupt Status/Clear Register.



typedef struct
hyplnkIntPendSetReg_s 
hyplnkIntPendSetReg_t
 Specification of the Hyperlink Interrupt Pending/Set Register.



typedef struct
hyplnkGenSoftIntReg_s 
hyplnkGenSoftIntReg_t
 Specification of the Hyperlink Generate Soft Interrupt Value Register.



typedef struct
hyplnkTXAddrOvlyReg_s 
hyplnkTXAddrOvlyReg_t
 Specification of the Tx Address Overlay Control Register.



typedef struct hyplnkRXAddrSelReg_s hyplnkRXAddrSelReg_t
 Specification of the Rx Address Selector Control Register.



typedef struct
hyplnkRXPrivIDIdxReg_s 
hyplnkRXPrivIDIdxReg_t
 Specification of the Rx Address PrivID Index Register.



typedef struct
hyplnkRXPrivIDValReg_s 
hyplnkRXPrivIDValReg_t
 Specification of the Rx Address PrivID Value Register.



typedef struct hyplnkRXSegIdxReg_s hyplnkRXSegIdxReg_t
 Specification of the Rx Address Segment Index Register.



typedef struct hyplnkRXSegValReg_s hyplnkRXSegValReg_t
 Specification of the Rx Address Segment Value Register.



typedef struct hyplnkChipVerReg_s hyplnkChipVerReg_t
 Specification of the Chip Version Register.



typedef struct
hyplnkLanePwrMgmtReg_s 
hyplnkLanePwrMgmtReg_t
 Specification of the Lane Power Management Control Register.



typedef struct hyplnkECCErrorsReg_s hyplnkECCErrorsReg_t
 Specification of the ECC Error Counters Register.



typedef struct
hyplnkLinkStatusReg_s 
hyplnkLinkStatusReg_t
 Specification of the Link Status Register.



typedef struct
hyplnkIntCtrlIdxReg_s 
hyplnkIntCtrlIdxReg_t
 Specification of the Interupt Control Index Register.



typedef struct
hyplnkIntCtrlValReg_s 
hyplnkIntCtrlValReg_t
 Specification of the Interrupt Control Value Register.



typedef struct hyplnkIntPtrIdxReg_s hyplnkIntPtrIdxReg_t
 Specification of the Interupt Control Index Register.



typedef struct hyplnkIntPtrValReg_s hyplnkIntPtrValReg_t
 Specification of the Interrupt Control Value Register.



typedef struct
hyplnkSERDESControl1Reg_s 
hyplnkSERDESControl1Reg_t
 Specification of the SerDes Control And Status 1 Register.



typedef struct
hyplnkSERDESControl2Reg_s 
hyplnkSERDESControl2Reg_t
 Specification of the SerDes Control And Status 2 Register.



typedef struct
hyplnkSERDESControl3Reg_s 
hyplnkSERDESControl3Reg_t
 Specification of the SerDes Control And Status 3 Register.



typedef struct
hyplnkSERDESControl4Reg_s 
hyplnkSERDESControl4Reg_t
 Specification of the SerDes Control And Status 4 Register.



typedef hyplnkRXPrivIDValReg_t hyplnkRXPrivIDTbl_t [hyplnk_RX_PRIVID_TBL_ENTS]
 Access to the entire RX PrivID table.



typedef hyplnkRXSegValReg_t hyplnkRXSegTbl_t [hyplnk_RX_SEG_TBL_ENTS]
 Access to the entire RX segment table.



typedef hyplnkIntCtrlValReg_t hyplnkIntCtrlTbl_t [hyplnk_INT_CTRL_TBL_ENTS]
 Access to the entire interrupt control table.



typedef hyplnkIntPtrValReg_t hyplnkIntPtrTbl_t [hyplnk_INT_PTR_TBL_ENTS]
 Access to the entire interrupt pointer table.

Typedef Documentation

Specification of the HyperLink Control Register.

The Control Register determines operation of the HyperLink module.

Specification of the ECC Error Counters Register.

The ECC Error Counter register counts the number of correctable single bit errors detected by the receive PLS as well as the number of detectable double bit errors. This value can be used to determine the integrity of the SerDes Rx signal. Writing to this register clears the current counts to zero.

Specification of the Hyperlink Generate Soft Interrupt Value Register.

The Generate Soft Interrupt Register should be written with a vector of the hardware index of the interrupt that is enabled for software interrupts. If the hyplnkIntCtrlValReg_s::iSec bit is also set, the csecure interface pin must be set to set the software interrupt. This register is also used to EOI Hyperlink_int_i hardware interrupts programmed in level mode.

Specification of the Interupt Control Index Register.

The Interrupt Control Index Register is used to control which hardware or software internal control register is read or written via hyplnkIntCtrlValReg_s.

Specification of the Interrupt Control Value Register.

The Interrupt Control Register reads or writes the associated fields to the intCtrlIdx interrupt channel. All channels not supported will return zero and be unsettable.

Specification of the Hyperlink Interrupt Pending/Set Register.

The Interrupt Pending/Set Register indicates the pending interrupt status. This register can be written by the local host or by remote interrupt packets when the hyplnkControlReg_s::int2cfg bit is set. When bits are set in this register, an interrupt output is signaled, if not already pending. Any write with a value of 0x0000 to this register will EOI the hyplnkIntPendSetReg_s interrupt output pins so they retrigger the interrupt. That is, writing a zero to hyplnkIntPendSetReg_s retriggers the output interrupt lines if any bits are still set in this register.

Specification of the Hyperlink Interrupt Priority Vector Status/Clear Register.

When read, the Interrupt Priority Vector Status/Clear register displays the highest priority vector with a pending interrupt. When writing, only intStat is valid, and the value represents the vector of the interrupt to be cleared.

Specification of the Interupt Control Index Register.

The Interrupt Pointer Index Register is used to control which Interrupt Pointer Register is read or written via hyplnkIntPtrIdxReg_s. The Interrupt Pointer Registers typically map to microprocessor interrupt controller set registers which get set to a one to interrupt that processor.

Specification of the Interrupt Control Value Register.

The Interrupt Pointer Value is used to write or read to the interrupt pointer number (intPtrIdx) This allows the remote interrupts to interrupt any MicroProcessor. Values written are stored in the Interrupt Pointer for that MicroProcessor.

Specification of the Hyperlink Interrupt Status/Clear Register.

The Interrupt Status/Clear Register indicates the unmasked interrupt status. Writing 1 to any bit in this register will clear the corresponding interrupt.

Specification of the Lane Power Management Control Register.

The Power Management Control Register configures how the HyperLink peripheral dynamically changes the number of lanes to save power.

Specification of the Link Status Register.

The Link status register is used to debug failed link conditions. It contains valuable information aoout the start of the link-state machines. It is used only to determine what might be causing the link failure. Because the source of this register can change quickly, this register updates only when a change has been detected and it is capable of transferring it to the bus clock domain.

Specification of the HyperLink Revision Register.

The Revision Register contains the major and minor revisions for the HyperLink module.

Specification of the Rx Address Selector Control Register.

The Rx Address Selector Control Register is used to configure which Rx Address bits select the Secure, PrivID and Segment/Length value arrays. This register also holds the secure value when the secure selection is one or zero.

address_translation_RX.jpg

Specification of the Rx Address Segment Value Register.

There is an array of 64 segment value registers. The particular segment value register accessed via hyplnkRXSegValReg_s is specified in hyplnkRXSegIdxReg_s::rxSegIdx.

After the segment index is extracted from the incoming address based on hyplnkRXAddrSelReg_s::rxSegSel, the index is dereferenced through this table to get a base address and length.

The local address (which will be presented through the SES or SMS MPAX) is constructed by:

((rxSegVal << 16) | RxAddress) & ((1 << (1 + rxLenVal)) - 1)

Specification of the SerDes Control And Status 1 Register.

The SerDes Control and Status 1 Register is used to define the mask time that the receive lane data is ignored after enabling the lane(s) from either a sleep or disabled state. The default numbers of these counters are not yet determined. When these counters are zero, there are no delays in link establishment. This register delays the start of link establishment or step up link by a number of symbol times sixteen.

Specification of the SerDes Control And Status 2 Register.

This register is Reserved for SerDes control and status operations. There is no defined functionality for this register.

Specification of the SerDes Control And Status 3 Register.

This register is Reserved for SerDes control and status operations. There is no defined functionality for this register.

Specification of the SerDes Control And Status 4 Register.

The SerDes Control and Status Register is used to quicken DV so that the periodic wake-up timer can be tested more easily and to allow change to the SerDes non-runtime power levels. The power-level controls were added to reduce SerDes sleep mode functionality risk. It provides the ability to enable or disable sleep functionality for both the transmit and receive SerDes lanes.

Specification of the HyperLink Status Register.

The Status Register is used to detect conditions that may be of interest to the system designer

Specification of the Tx Address Overlay Control Register.

The Tx Address Map Mask Register is used to trim the transmitted packet address to remote device VBUSM addresses.


Copyright 2012, Texas Instruments Incorporated