pcieType1BusNumReg_s Struct Reference
[PCIE LLD Type1 (root) Register Definitions]

Specification of the Latency Timer and Bus Number Register. More...

#include <pcie.h>

Data Fields

uint32_t raw
 [ro] Raw image of register on read; actual value on write
uint8_t secLatTmr
 [ro] Secondary Latency Timer (N/A for PCIe)
uint8_t subBusNum
 [rw] Subordinate Bus Number. This is highest bus number on downstream interface.
uint8_t secBusNum
 [rw] Secondary Bus Number. It is typically 1h for RC.
uint8_t priBusNum
 [rw] Primary Bus Number. It is 0 for RC and nonzero for switch devices only.

Detailed Description

Specification of the Latency Timer and Bus Number Register.


Field Documentation

[rw] Primary Bus Number. It is 0 for RC and nonzero for switch devices only.

Field size: 8 bits

[rw] Secondary Bus Number. It is typically 1h for RC.

Field size: 8 bits

[ro] Secondary Latency Timer (N/A for PCIe)

Field size: 8 bits

[rw] Subordinate Bus Number. This is highest bus number on downstream interface.

Field size: 8 bits


The documentation for this struct was generated from the following file:

Copyright 2012, Texas Instruments Incorporated