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Functions | |
CSL_Status | CSL_edma3Init (CSL_Edma3Context *pContext) |
CSL_Edma3Handle | CSL_edma3Open (CSL_Edma3Obj *edmaObj, CSL_InstNum edmaNum, CSL_Edma3ModuleAttr *attr, CSL_Status *status) |
CSL_Status | CSL_edma3Close (CSL_Edma3Handle hEdma) |
CSL_Status | CSL_edma3HwSetup (CSL_Edma3Handle hMod, CSL_Edma3HwSetup *setup) |
CSL_Status | CSL_edma3GetHwSetup (CSL_Edma3Handle hMod, CSL_Edma3HwSetup *setup) |
CSL_Status | CSL_edma3HwControl (CSL_Edma3Handle hMod, CSL_Edma3HwControlCmd cmd, void *cmdArg) |
CSL_Status | CSL_edma3ccGetModuleBaseAddr (CSL_InstNum edmaNum, CSL_Edma3ModuleAttr *pAttr, CSL_Edma3ModuleBaseAddress *pBaseAddress, CSL_Edma3CfgInfo *pCfgInfo) |
CSL_Status | CSL_edma3GetHwStatus (CSL_Edma3Handle hMod, CSL_Edma3HwStatusQuery myQuery, void *response) |
CSL_Edma3ChannelHandle | CSL_edma3ChannelOpen (CSL_Edma3ChannelObj *edmaObj, CSL_InstNum edmaNum, CSL_Edma3ChannelAttr *chAttr, CSL_Status *status) |
CSL_Status | CSL_edma3ChannelClose (CSL_Edma3ChannelHandle hEdma) |
CSL_Status | CSL_edma3HwChannelSetupParam (CSL_Edma3ChannelHandle hEdma, Uint16 paramNum) |
CSL_Status | CSL_edma3HwChannelSetupTriggerWord (CSL_Edma3ChannelHandle hEdma, Uint8 triggerWord) |
CSL_Status | CSL_edma3HwChannelSetupQue (CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que que) |
CSL_Status | CSL_edma3GetHwChannelSetupParam (CSL_Edma3ChannelHandle hEdma, Uint16 *paramNum) |
CSL_Status | CSL_edma3GetHwChannelSetupTriggerWord (CSL_Edma3ChannelHandle hEdma, Uint8 *triggerWord) |
CSL_Status | CSL_edma3GetHwChannelSetupQue (CSL_Edma3ChannelHandle hEdma, CSL_Edma3Que *que) |
CSL_Status | CSL_edma3HwChannelControl (CSL_Edma3ChannelHandle hCh, CSL_Edma3HwChannelControlCmd cmd, void *cmdArg) |
CSL_Status | CSL_edma3GetHwChannelStatus (CSL_Edma3ChannelHandle hCh, CSL_Edma3HwChannelStatusQuery myQuery, void *response) |
CSL_Edma3ParamHandle | CSL_edma3GetParamHandle (CSL_Edma3ChannelHandle hEdma, Int16 paramNum, CSL_Status *status) |
CSL_Status | CSL_edma3ParamSetup (CSL_Edma3ParamHandle hParam, CSL_Edma3ParamSetup *pSetup) |
CSL_Status | CSL_edma3ParamWriteWord (CSL_Edma3ParamHandle hParamHndl, Uint16 wordOffset, Uint32 word) |
CSL_IDEF_INLINE void | CSL_edma3GetInfo (CSL_Edma3Handle hModule, CSL_Edma3QueryInfo *response) |
CSL_IDEF_INLINE void | CSL_edma3MapDMAChannelToParamBlock (CSL_Edma3Handle hModule, Uint8 dmaChannel, Uint16 paramId) |
CSL_IDEF_INLINE Uint16 | CSL_edma3GetDMAChannelToParamBlockMapping (CSL_Edma3Handle hModule, Uint8 dmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3MapQDMAChannelToParamBlock (CSL_Edma3Handle hModule, Uint8 qdmaChannel, Uint16 paramId) |
CSL_IDEF_INLINE Uint16 | CSL_edma3GetQDMAChannelToParamBlockMapping (CSL_Edma3Handle hModule, Uint8 qdmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3SetQDMATriggerWord (CSL_Edma3Handle hModule, Uint8 qdmaChannel, Uint8 trword) |
CSL_IDEF_INLINE void | CSL_edma3GetQDMATriggerWord (CSL_Edma3Handle hModule, Uint8 qdmaChannel, Uint8 *trword) |
CSL_IDEF_INLINE void | CSL_edma3MapDMAChannelToEventQueue (CSL_Edma3Handle hModule, Uint8 dmaChannel, Uint8 eventQueue) |
CSL_IDEF_INLINE Uint8 | CSL_edma3GetDMAChannelToEventQueueMapping (CSL_Edma3Handle hModule, Uint8 dmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3MapQDMAChannelToEventQueue (CSL_Edma3Handle hModule, Uint8 qdmaChannel, Uint8 eventQueue) |
CSL_IDEF_INLINE Uint8 | CSL_edma3GetQDMAChannelToEventQueueMapping (CSL_Edma3Handle hModule, Uint8 qdmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3MapEventQueueToTC (CSL_Edma3Handle hModule, Uint8 eventQueue, Uint8 tcNum) |
CSL_IDEF_INLINE Uint8 | CSL_edma3GetEventQueueToTCMapping (CSL_Edma3Handle hModule, Uint8 eventQueue) |
CSL_IDEF_INLINE void | CSL_edma3SetEventQueuePriority (CSL_Edma3Handle hModule, Uint8 eventQueue, Uint8 priority) |
CSL_IDEF_INLINE Uint8 | CSL_edma3GetEventQueuePriority (CSL_Edma3Handle hModule, Uint8 eventQueue) |
CSL_IDEF_INLINE void | CSL_edma3GetEventMissed (CSL_Edma3Handle hModule, CSL_BitMask32 *missedLo, CSL_BitMask32 *missedHi, CSL_BitMask32 *missedQdma) |
CSL_IDEF_INLINE void | CSL_edma3IsDMAChannelMissedEventSet (CSL_Edma3Handle hModule, Uint8 dmaChannel, Bool *response) |
CSL_IDEF_INLINE void | CSL_edma3IsQDMAChannelMissedEventSet (CSL_Edma3Handle hModule, Uint8 qdmaChannel, Bool *response) |
CSL_IDEF_INLINE void | CSL_edma3EventsMissedClear (CSL_Edma3Handle hModule, CSL_BitMask32 missedLo, CSL_BitMask32 missedHi, CSL_BitMask32 missedQdma) |
CSL_IDEF_INLINE void | CSL_edma3ClearDMAMissedEvent (CSL_Edma3Handle hModule, Uint8 dmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3ClearQDMAMissedEvent (CSL_Edma3Handle hModule, Uint8 qdmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3GetControllerError (CSL_Edma3Handle hModule, CSL_Edma3CtrlErrStat *ccStat) |
CSL_IDEF_INLINE void | CSL_edma3ClearControllerError (CSL_Edma3Handle hModule, CSL_Edma3CtrlErrStat *ccStat) |
CSL_IDEF_INLINE void | CSL_edma3ErrorEval (CSL_Edma3Handle hModule) |
CSL_IDEF_INLINE void | CSL_edma3DmaRegionAccessEnable (CSL_Edma3Handle hModule, Int edmaRegion, CSL_BitMask32 drae, CSL_BitMask32 draeh) |
CSL_IDEF_INLINE void | CSL_edma3DmaRegionAccessDisable (CSL_Edma3Handle hModule, Int edmaRegion, CSL_BitMask32 drae, CSL_BitMask32 draeh) |
CSL_IDEF_INLINE void | CSL_edma3QdmaRegionAccessEnable (CSL_Edma3Handle hModule, Int edmaRegion, CSL_BitMask32 qrae) |
CSL_IDEF_INLINE void | CSL_edma3QdmaRegionAccessDisable (CSL_Edma3Handle hModule, Int edmaRegion, CSL_BitMask32 qrae) |
CSL_IDEF_INLINE void | CSL_edma3GetWaterMark (CSL_Edma3Handle hModule, Uint8 eventQueue, Uint8 *waterMark) |
CSL_IDEF_INLINE void | CSL_edma3GetNumberValidEntries (CSL_Edma3Handle hModule, Uint8 eventQueue, Uint8 *numValidEntries) |
CSL_IDEF_INLINE void | CSL_edma3GetStartPointer (CSL_Edma3Handle hModule, Uint8 eventQueue, Uint8 *startPtr) |
CSL_IDEF_INLINE void | CSL_edma3GetThresholdExceeded (CSL_Edma3Handle hModule, Uint8 eventQueue, Bool *thresholdExceeded) |
CSL_IDEF_INLINE void | CSL_edma3EventQueueThresholdSet (CSL_Edma3Handle hModule, Uint8 eventQueue, Uint8 threshold) |
CSL_IDEF_INLINE void | CSL_edma3GetActivityStatus (CSL_Edma3Handle hModule, CSL_Edma3ActivityStat *activityStat) |
CSL_IDEF_INLINE void | CSL_edma3GetMemoryFaultError (CSL_Edma3Handle hModule, CSL_Edma3MemFaultStat *memFault) |
CSL_IDEF_INLINE void | CSL_edma3MemFaultClear (CSL_Edma3Handle hModule) |
CSL_IDEF_INLINE void | CSL_edma3GetMemoryProtectionAttrib (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 *mppa) |
CSL_IDEF_INLINE void | CSL_edma3SetMemoryProtectionAttrib (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 mppa) |
CSL_IDEF_INLINE void | CSL_edma3IsDMAChannelEventPending (CSL_Edma3Handle hModule, Uint8 dmaChannel, Bool *response) |
CSL_IDEF_INLINE void | CSL_edma3ClearDMAChannelEvent (CSL_Edma3Handle hModule, Int region, Uint8 dmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3SetDMAChannelEvent (CSL_Edma3Handle hModule, Int region, Uint8 dmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3DMAChannelDisable (CSL_Edma3Handle hModule, Int region, Uint8 dmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3DMAChannelEnable (CSL_Edma3Handle hModule, Int region, Uint8 dmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3GetDMASecondaryEvents (CSL_Edma3Handle hModule, CSL_BitMask32 *secEventLo, CSL_BitMask32 *secEventHi) |
CSL_IDEF_INLINE void | CSL_edma3IsDMAChannelSecondaryEventSet (CSL_Edma3Handle hModule, Uint8 dmaChannel, Bool *response) |
CSL_IDEF_INLINE void | CSL_edma3ClearDMASecondaryEvents (CSL_Edma3Handle hModule, CSL_BitMask32 secEventLo, CSL_BitMask32 secEventHi) |
CSL_IDEF_INLINE void | CSL_edma3ClearDMAChannelSecondaryEvents (CSL_Edma3Handle hModule, Uint8 dmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3InterruptLoDisable (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 intrLo) |
CSL_IDEF_INLINE void | CSL_edma3InterruptHiDisable (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 intrHi) |
CSL_IDEF_INLINE void | CSL_edma3InterruptLoEnable (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 intrLo) |
CSL_IDEF_INLINE void | CSL_edma3InterruptHiEnable (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 intrHi) |
CSL_IDEF_INLINE void | CSL_edma3GetLoPendingInterrupts (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 *intrLo) |
CSL_IDEF_INLINE void | CSL_edma3GetHiPendingInterrupts (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 *intrHi) |
CSL_IDEF_INLINE void | CSL_edma3ClearLoPendingInterrupts (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 intrLo) |
CSL_IDEF_INLINE void | CSL_edma3ClearHiPendingInterrupts (CSL_Edma3Handle hModule, Int region, CSL_BitMask32 intrHi) |
CSL_IDEF_INLINE void | CSL_edma3InterruptEval (CSL_Edma3Handle hModule, Int region) |
CSL_IDEF_INLINE void | CSL_edma3IsQDMAChannelEventPending (CSL_Edma3Handle hModule, Uint8 qdmaChannel, Bool *response) |
CSL_IDEF_INLINE void | CSL_edma3QDMAChannelEnable (CSL_Edma3Handle hModule, Int region, Uint8 qdmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3QDMAChannelDisable (CSL_Edma3Handle hModule, Int region, Uint8 qdmaChannel) |
CSL_IDEF_INLINE void | CSL_edma3GetQDMASecondaryEvents (CSL_Edma3Handle hModule, Uint32 *qdmaSecEvent) |
CSL_IDEF_INLINE void | CSL_edma3IsQDMAChannelSecondaryEventSet (CSL_Edma3Handle hModule, Uint8 qdmaChannel, Bool *response) |
CSL_IDEF_INLINE void | CSL_edma3ClearQDMASecondaryEvents (CSL_Edma3Handle hModule, Uint32 qdmaSecEvent) |
CSL_IDEF_INLINE void | CSL_edma3ClearQDMAChannelSecondaryEvents (CSL_Edma3Handle hModule, Uint8 qdmaChannel) |
CSL_Status CSL_edma3ccGetModuleBaseAddr | ( | CSL_InstNum | edmaNum, | |
CSL_Edma3ModuleAttr * | pParam, | |||
CSL_Edma3ModuleBaseAddress * | pBaseAddress, | |||
CSL_Edma3CfgInfo * | pCfgInfo | |||
) |
============================================================================
CSL_edma3ccGetModuleBaseAddr
Description
This function is used for getting the base-address of the peripheral instance. This function will be called inside the @ CSL_edma3Open()/ CSL_edma3ChannelOpen() function call.
Note: This function is open for re-implementing if the user wants to modify the base address of the peripheral object to point to a different location and there by allow CSL initiated write/reads into peripheral MMR's go to an alternate location.
Arguments
edmaNum Specifies the instance of the edma to be opened. pParam Module specific parameters. pBaseAddress Pointer to baseaddress structure containing base address details. pCfgInfo Pointer to the EDMA CC Instance information populated by this API.
Return Value
Success - CSL_SOK
Error - CSL_ESYS_FAIL (Timer Instance is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Pre Condition
None
Post Condition
Base Address structure is populated
Affects
None.
Example
CSL_Status status; CSL_Edma3ModuleBaseAddress baseAddress; CSL_Edma3CfgInfo cfgInfo; // Get the EDMA CC Instance 0 Information status = CSL_edma3ccGetModuleBaseAddr(0, NULL, &baseAddress, &cfgInfo);
===========================================================================
CSL_Status CSL_edma3ChannelClose | ( | CSL_Edma3ChannelHandle | hEdma | ) |
============================================================================
csl_edma3ChannelClose.c
Description
This function marks the channel cannot be accessed anymore using the handle. CSL for the EDMA channel need to be reopened before using any edma channel.
Arguments
hEdma Handle to the channel to be closed.
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open(), CSL_edma3ChannelOpen() must be invoked successfully in that order before this API can be invoked.
Post Condition
The edma channel related CSL APIs can not be called until the edma channel is reopened again using CSL_edma3ChannelOpen()
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, 0, NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 0; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ... // Close Channel CSL_edma3ChannelClose(hChannel); ...
=============================================================================
CSL_Edma3ChannelHandle CSL_edma3ChannelOpen | ( | CSL_Edma3ChannelObj * | pEdmaObj, | |
CSL_InstNum | edmaNum, | |||
CSL_Edma3ChannelAttr * | pChAttr, | |||
CSL_Status * | pStatus | |||
) |
============================================================================
CSL_edma3ChannelOpen
Description
The API returns a handle for the specified EDMA Channel for use. The channel can be re-opened anytime after it has been normally closed if so required. The handle returned by this call is input as an essential argument for many of the APIs described for this module.
Arguments
pEdmaObj pointer to the object that holds reference to the channel instance of the Specified DMA edmaNum Instance of EDMA whose channel is requested pChAttr Channel Attributes which describe the channel to be opened. status Status of the function call
Return Value
Success - Channel Handle
Error - NULL
Pre Condition
CSL_edma3Init(), CSL_edma3Open() must be invoked successfully in that order before this API can be invoked
Post Condition EDMA channel object structure is populated
Affects
None
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, 0, NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 0; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ...
=============================================================================
CSL_IDEF_INLINE void CSL_edma3ClearControllerError | ( | CSL_Edma3Handle | hModule, | |
CSL_Edma3CtrlErrStat * | ccStat | |||
) |
============================================================================
CSL_edma3ClearControllerError
Description
Channel Controller Error Fault.
Arguments
hModule Module Handle ccStat Error Status which is to be cleared.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_CCERRCLR_QTHRXD0;TPCC_TPCC_CCERRCLR_QTHRXD1;TPCC_TPCC_CCERRCLR_QTHRXD2; TPCC_TPCC_CCERRCLR_QTHRXD3;TPCC_TPCC_CCERRCLR_QTHRXD4;TPCC_TPCC_CCERRCLR_QTHRXD5; TPCC_TPCC_CCERRCLR_QTHRXD6;TPCC_TPCC_CCERRCLR_QTHRXD7, TPCC_TPCC_CCERR_TCCERR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3CtrlErrStat ccError; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get Controller Error status = CSL_edma3GetControllerError(hModule,&ccError); ... // Clear the error. CSL_edma3ClearControllerError(hModule,&ccError); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearDMAChannelEvent | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
Uint8 | dmaChannel | |||
) |
============================================================================
CSL_edma3ClearDMAChannelEvent
Description
This API clears the event for the specific DMA channel.
Arguments
hModule Module Handle region Region (Shadow or Global) dmaChannel DMA Channel for which the event is cleared.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_ECR_E0=1;TPCC_TPCC_ECR_E1=1;TPCC_TPCC_ECR_E2=1;TPCC_TPCC_ECR_E3=1; TPCC_TPCC_ECR_E4=1;TPCC_TPCC_ECR_E5=1;TPCC_TPCC_ECR_E6=1;TPCC_TPCC_ECR_E7=1; TPCC_TPCC_ECR_E8=1;TPCC_TPCC_ECR_E9=1;TPCC_TPCC_ECR_E10=1;TPCC_TPCC_ECR_E11=1; TPCC_TPCC_ECR_E12=1;TPCC_TPCC_ECR_E13=1;TPCC_TPCC_ECR_E14=1;TPCC_TPCC_ECR_E15=1; TPCC_TPCC_ECR_E16=1;TPCC_TPCC_ECR_E17=1;TPCC_TPCC_ECR_E18=1;TPCC_TPCC_ECR_E19=1; TPCC_TPCC_ECR_E20=1;TPCC_TPCC_ECR_E21=1;TPCC_TPCC_ECR_E22=1;TPCC_TPCC_ECR_E23=1; TPCC_TPCC_ECR_E24=1;TPCC_TPCC_ECR_E25=1;TPCC_TPCC_ECR_E26=1;TPCC_TPCC_ECR_E27=1; TPCC_TPCC_ECR_E28=1;TPCC_TPCC_ECR_E29=1;TPCC_TPCC_ECR_E30=1;TPCC_TPCC_ECR_E31=1;
TPCC_TPCC_ECRH_E32=1;TPCC_TPCC_ECRH_E33=1;TPCC_TPCC_ECRH_E34=1;TPCC_TPCC_ECRH_E35=1; TPCC_TPCC_ECRH_E36=1;TPCC_TPCC_ECRH_E37=1;TPCC_TPCC_ECRH_E38=1;TPCC_TPCC_ECRH_E39=1; TPCC_TPCC_ECRH_E40=1;TPCC_TPCC_ECRH_E41=1;TPCC_TPCC_ECRH_E42=1;TPCC_TPCC_ECRH_E43=1; TPCC_TPCC_ECRH_E44=1;TPCC_TPCC_ECRH_E45=1;TPCC_TPCC_ECRH_E46=1;TPCC_TPCC_ECRH_E47=1; TPCC_TPCC_ECRH_E48=1;TPCC_TPCC_ECRH_E49=1;TPCC_TPCC_ECRH_E50=1;TPCC_TPCC_ECRH_E51=1; TPCC_TPCC_ECRH_E52=1;TPCC_TPCC_ECRH_E53=1;TPCC_TPCC_ECRH_E54=1;TPCC_TPCC_ECRH_E55=1; TPCC_TPCC_ECRH_E56=1;TPCC_TPCC_ECRH_E57=1;TPCC_TPCC_ECRH_E58=1;TPCC_TPCC_ECRH_E59=1; TPCC_TPCC_ECRH_E60=1;TPCC_TPCC_ECRH_E61=1;TPCC_TPCC_ECRH_E62=1;TPCC_TPCC_ECRH_E63=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Bool dmaStatus; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get DMA Channel 0 Status CSL_edma3GetDMAChannelEvent(hModule, 0, &dmaStatus); if (dmaStatus == TRUE) { // DMA Channel 0 is active... ... // Clear DMA Channel 0. CSL_edma3ClearDMAChannelEvent (hModule, CSL_EDMA3_REGION_GLOBAL, 0); }
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearDMAChannelSecondaryEvents | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel | |||
) |
============================================================================
CSL_edma3ClearDMAChannelSecondaryEvents
Description
This API clears the DMA Secondary Event for a specific DMA Channel.
Arguments
hModule Module Handle qdmaChannel DMA Channel for which the secondary event is to be cleared.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_SECR_SECR0=1;TPCC_TPCC_SECR_SECR1=1;TPCC_TPCC_SECR_SECR2=1; TPCC_TPCC_SECR_SECR3=1;TPCC_TPCC_SECR_SECR4=1;TPCC_TPCC_SECR_SECR5=1; TPCC_TPCC_SECR_SECR6=1;TPCC_TPCC_SECR_SECR7=1;TPCC_TPCC_SECR_SECR8=1; TPCC_TPCC_SECR_SECR9=1;TPCC_TPCC_SECR_SECR10=1;TPCC_TPCC_SECR_SECR11=1; TPCC_TPCC_SECR_SECR12=1;TPCC_TPCC_SECR_SECR13=1;TPCC_TPCC_SECR_SECR14=1; TPCC_TPCC_SECR_SECR15=1;TPCC_TPCC_SECR_SECR16=1;TPCC_TPCC_SECR_SECR17=1; TPCC_TPCC_SECR_SECR18=1;TPCC_TPCC_SECR_SECR19=1;TPCC_TPCC_SECR_SECR20=1; TPCC_TPCC_SECR_SECR21=1;TPCC_TPCC_SECR_SECR22=1;TPCC_TPCC_SECR_SECR23=1; TPCC_TPCC_SECR_SECR24=1;TPCC_TPCC_SECR_SECR25=1;TPCC_TPCC_SECR_SECR26=1; TPCC_TPCC_SECR_SECR27=1;TPCC_TPCC_SECR_SECR28=1;TPCC_TPCC_SECR_SECR29=1; TPCC_TPCC_SECR_SECR30=1;TPCC_TPCC_SECR_SECR31=1;
TPCC_TPCC_SECRH_SECR32=1;TPCC_TPCC_SECRH_SECR33=1;TPCC_TPCC_SECRH_SECR34=1; TPCC_TPCC_SECRH_SECR35=1;TPCC_TPCC_SECRH_SECR36=1;TPCC_TPCC_SECRH_SECR37=1; TPCC_TPCC_SECRH_SECR38=1;TPCC_TPCC_SECRH_SECR39=1;TPCC_TPCC_SECRH_SECR40=1; TPCC_TPCC_SECRH_SECR41=1;TPCC_TPCC_SECRH_SECR42=1;TPCC_TPCC_SECRH_SECR43=1; TPCC_TPCC_SECRH_SECR44=1;TPCC_TPCC_SECRH_SECR45=1;TPCC_TPCC_SECRH_SECR46=1; TPCC_TPCC_SECRH_SECR47=1;TPCC_TPCC_SECRH_SECR48=1;TPCC_TPCC_SECRH_SECR49=1; TPCC_TPCC_SECRH_SECR50=1;TPCC_TPCC_SECRH_SECR51=1;TPCC_TPCC_SECRH_SECR52=1; TPCC_TPCC_SECRH_SECR53=1;TPCC_TPCC_SECRH_SECR54=1;TPCC_TPCC_SECRH_SECR55=1; TPCC_TPCC_SECRH_SECR56=1;TPCC_TPCC_SECRH_SECR57=1;TPCC_TPCC_SECRH_SECR58=1; TPCC_TPCC_SECRH_SECR59=1;TPCC_TPCC_SECRH_SECR60=1;TPCC_TPCC_SECRH_SECR61=1; TPCC_TPCC_SECRH_SECR62=1;TPCC_TPCC_SECRH_SECR63=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; Uint32 qdmaSecEvent; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Clear the DMA Secondary Event for DMA channel 1 CSL_edma3ClearDMAChannelSecondaryEvents(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearDMAMissedEvent | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel | |||
) |
============================================================================
CSL_edma3ClearDMAMissedEvent
Description
The API clears the missed event for the specific DMA Channel.
Arguments
hModule Module Handle dmaChannel DMA Channel for which the event is cleared.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
Clears all the missed events
Writes
TPCC_TPCC_EMCR_EMCR0;TPCC_TPCC_EMCR_EMCR1;TPCC_TPCC_EMCR_EMCR2; TPCC_TPCC_EMCR_EMCR3;TPCC_TPCC_EMCR_EMCR4;TPCC_TPCC_EMCR_EMCR5; TPCC_TPCC_EMCR_EMCR6;TPCC_TPCC_EMCR_EMCR7;TPCC_TPCC_EMCR_EMCR8; TPCC_TPCC_EMCR_EMCR9;TPCC_TPCC_EMCR_EMCR10;TPCC_TPCC_EMCR_EMCR11; TPCC_TPCC_EMCR_EMCR12;TPCC_TPCC_EMCR_EMCR13;TPCC_TPCC_EMCR_EMCR14; TPCC_TPCC_EMCR_EMCR15;TPCC_TPCC_EMCR_EMCR16;TPCC_TPCC_EMCR_EMCR17; TPCC_TPCC_EMCR_EMCR18;TPCC_TPCC_EMCR_EMCR19;TPCC_TPCC_EMCR_EMCR20; TPCC_TPCC_EMCR_EMCR21;TPCC_TPCC_EMCR_EMCR22;TPCC_TPCC_EMCR_EMCR23; TPCC_TPCC_EMCR_EMCR24;TPCC_TPCC_EMCR_EMCR25;TPCC_TPCC_EMCR_EMCR26; TPCC_TPCC_EMCR_EMCR27;TPCC_TPCC_EMCR_EMCR28;TPCC_TPCC_EMCR_EMCR29; TPCC_TPCC_EMCR_EMCR30;TPCC_TPCC_EMCR_EMCR31; TPCC_TPCC_EMCRH_EMCR32;TPCC_TPCC_EMCRH_EMCR33;TPCC_TPCC_EMCRH_EMCR34 TPCC_TPCC_EMCRH_EMCR35;TPCC_TPCC_EMCRH_EMCR36;TPCC_TPCC_EMCRH_EMCR37 TPCC_TPCC_EMCRH_EMCR38;TPCC_TPCC_EMCRH_EMCR39;TPCC_TPCC_EMCRH_EMCR40 TPCC_TPCC_EMCRH_EMCR41;TPCC_TPCC_EMCRH_EMCR42;TPCC_TPCC_EMCRH_EMCR43 TPCC_TPCC_EMCRH_EMCR44;TPCC_TPCC_EMCRH_EMCR45;TPCC_TPCC_EMCRH_EMCR46 TPCC_TPCC_EMCRH_EMCR47;TPCC_TPCC_EMCRH_EMCR48;TPCC_TPCC_EMCRH_EMCR49 TPCC_TPCC_EMCRH_EMCR50;TPCC_TPCC_EMCRH_EMCR51;TPCC_TPCC_EMCRH_EMCR52 TPCC_TPCC_EMCRH_EMCR53;TPCC_TPCC_EMCRH_EMCR54;TPCC_TPCC_EMCRH_EMCR55 TPCC_TPCC_EMCRH_EMCR56;TPCC_TPCC_EMCRH_EMCR57;TPCC_TPCC_EMCRH_EMCR58 TPCC_TPCC_EMCRH_EMCR59;TPCC_TPCC_EMCRH_EMCR60;TPCC_TPCC_EMCRH_EMCR61 TPCC_TPCC_EMCRH_EMCR62;TPCC_TPCC_EMCRH_EMCR63;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 missedLo, missedHi, missedQdma; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Clear missed DMA 1 channel event. CSL_edma3ClearDMAMissedEvent(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearDMASecondaryEvents | ( | CSL_Edma3Handle | hModule, | |
CSL_BitMask32 | secEventLo, | |||
CSL_BitMask32 | secEventHi | |||
) |
============================================================================
CSL_edma3ClearDMASecondaryEvents
Description
This API clears the DMA secondary events
Arguments
hModule Module Handle secEventLo Lower order 32 bits of secondary events to be cleared secEventHi Higher order 32 bits of secondary events to be cleared
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_SECR,TPCC_TPCC_SECRH
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 secEventLo; CSL_BitMask32 secEventHi; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Get the DMA Secondary Events. CSL_edma3GetDMASecondaryEvents(hModule, &secEventLo, &secEventHi); ... // Clear the DMA Secondary Events CSL_edma3ClearDMASecondaryEvents(hModule, secEventLo, secEventHi);
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearHiPendingInterrupts | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 | intrHi | |||
) |
============================================================================
CSL_edma3ClearHiPendingInterrupts
Description
This API clears the High pending interrupts using the interrupt bitmasks provided
Arguments
hModule Module Handle region Region (Shadown Region or Global) intrHi Interrupt 32-63 (BitMask32) to be cleared
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_ICRH
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 edmaIntrHi; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get all the pending interrupts for the global region. CSL_edma3GetHiPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, &edmaIntrHi); ... // Clear the pending interrupts for the global region. CSL_edma3ClearHiPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, edmaIntrHi);
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearLoPendingInterrupts | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 | intrLo | |||
) |
============================================================================
CSL_edma3ClearLoPendingInterrupts
Description
This API clears the low pending interrupts using the interrupt bitmasks provided
Arguments
hModule Module Handle region Region (Shadown Region or Global) intrLo Interrupt 0-31 (BitMask32) to be cleared
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_ICR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 edmaIntrLo; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get all the pending interrupts for the global region. CSL_edma3GetLoPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, &edmaIntrLo); ... // Clear the pending interrupts for the global region. CSL_edma3ClearLoPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, edmaIntrLo);
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearQDMAChannelSecondaryEvents | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel | |||
) |
============================================================================
CSL_edma3ClearQDMAChannelSecondaryEvents
Description
This API clears the QDMA Secondary Event for a specific QDMA Channel.
Arguments
hModule Module Handle qdmaChannel QDMA Channel for which the secondary event is to be cleared.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_QSECR_QSECR0=1;TPCC_TPCC_QSECR_QSECR1=1;TPCC_TPCC_QSECR_QSECR2=1; TPCC_TPCC_QSECR_QSECR3=1;TPCC_TPCC_QSECR_QSECR4=1;TPCC_TPCC_QSECR_QSECR5=1; TPCC_TPCC_QSECR_QSECR6=1;TPCC_TPCC_QSECR_QSECR7=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; Uint32 qdmaSecEvent; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Clear the QDMA Secondary Event for QDMA channel 1 CSL_edma3ClearQDMAChannelSecondaryEvents(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearQDMAMissedEvent | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel | |||
) |
============================================================================
CSL_edma3ClearQDMAMissedEvent
Description
The API clears the missed event for the specific QDMA Channel.
Arguments
hModule Module Handle qdmaChannel QDMA Channel for which the event is cleared.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
Clears all the missed events
Writes
TPCC_TPCC_QEMCR_QEMCR0;TPCC_TPCC_QEMCR_QEMCR1;TPCC_TPCC_QEMCR_QEMCR2; TPCC_TPCC_QEMCR_QEMCR3;TPCC_TPCC_QEMCR_QEMCR4;TPCC_TPCC_QEMCR_QEMCR5; TPCC_TPCC_QEMCR_QEMCR6;TPCC_TPCC_QEMCR_QEMCR7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 missedLo, missedHi, missedQdma; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Clear missed QDMA Channel 1 event. CSL_edma3ClearQDMAMissedEvent(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ClearQDMASecondaryEvents | ( | CSL_Edma3Handle | hModule, | |
Uint32 | qdmaSecEvent | |||
) |
============================================================================
CSL_edma3ClearQDMASecondaryEvents
Description
This API clears the QDMA Secondary Event.
Arguments
hModule Module Handle qdmaSecEvent QDMA Secondary Event to be cleared.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_QSECR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; Uint32 qdmaSecEvent; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get the QDMA Secondary Event CSL_edma3GetQDMASecondaryEvents(hModule, &qdmaSecEvent); ... // Clear the QDMA Secondary Event CSL_edma3ClearQDMASecondaryEvents(hModule, qdmaSecEvent); ...
===========================================================================
CSL_Status CSL_edma3Close | ( | CSL_Edma3Handle | hEdma | ) |
============================================================================
CSL_edma3Close.c
Description
This is a module level close require to invalidate the module handle. The module handle must not be used after this API call.
Arguments
hEdma Handle to the Edma Instance
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Pre Condition
Functions CSL_edma3Init() and CSL_edma3Open() have to be called in that order successfully before calling this function.
Post Condition
The edma CSL APIs can not be called until the edma CSL is reopened again using CSL_edma3Open()
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); ... // Close the Module. CSL_edma3Close(hModule); ...
=============================================================================
CSL_IDEF_INLINE void CSL_edma3DMAChannelDisable | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
Uint8 | dmaChannel | |||
) |
============================================================================
CSL_edma3DMAChannelDisable
Description
This API disables the specified DMA Channel.
Arguments
hModule Module Handle region Region (Shadow or Global) dmaChannel DMA Channel to be disabled.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_EECR_E0=1;TPCC_TPCC_EECR_E1=1;TPCC_TPCC_EECR_E2=1; TPCC_TPCC_EECR_E3=1;TPCC_TPCC_EECR_E4=1;TPCC_TPCC_EECR_E5=1; TPCC_TPCC_EECR_E6=1;TPCC_TPCC_EECR_E7=1;TPCC_TPCC_EECR_E8=1; TPCC_TPCC_EECR_E9=1;TPCC_TPCC_EECR_E10=1;TPCC_TPCC_EECR_E11=1; TPCC_TPCC_EECR_E12=1;TPCC_TPCC_EECR_E13=1;TPCC_TPCC_EECR_E14=1; TPCC_TPCC_EECR_E15=1;TPCC_TPCC_EECR_E16=1;TPCC_TPCC_EECR_E17=1; TPCC_TPCC_EECR_E18=1;TPCC_TPCC_EECR_E19=1;TPCC_TPCC_EECR_E20=1; TPCC_TPCC_EECR_E21=1;TPCC_TPCC_EECR_E22=1;TPCC_TPCC_EECR_E23=1; TPCC_TPCC_EECR_E24=1;TPCC_TPCC_EECR_E25=1;TPCC_TPCC_EECR_E26=1; TPCC_TPCC_EECR_E27=1;TPCC_TPCC_EECR_E28=1;TPCC_TPCC_EECR_E29=1; TPCC_TPCC_EECR_E30=1;TPCC_TPCC_EECR_E31=1;
TPCC_TPCC_EECRH_E32=1;TPCC_TPCC_EECRH_E33=1;TPCC_TPCC_EECRH_E34=1; TPCC_TPCC_EECRH_E35=1;TPCC_TPCC_EECRH_E36=1;TPCC_TPCC_EECRH_E37=1; TPCC_TPCC_EECRH_E38=1;TPCC_TPCC_EECRH_E39=1;TPCC_TPCC_EECRH_E40=1; TPCC_TPCC_EECRH_E41=1;TPCC_TPCC_EECRH_E42=1;TPCC_TPCC_EECRH_E43=1; TPCC_TPCC_EECRH_E44=1;TPCC_TPCC_EECRH_E45=1;TPCC_TPCC_EECRH_E46=1; TPCC_TPCC_EECRH_E47=1;TPCC_TPCC_EECRH_E48=1;TPCC_TPCC_EECRH_E49=1; TPCC_TPCC_EECRH_E50=1;TPCC_TPCC_EECRH_E51=1;TPCC_TPCC_EECRH_E52=1; TPCC_TPCC_EECRH_E53=1;TPCC_TPCC_EECRH_E54=1;TPCC_TPCC_EECRH_E55=1; TPCC_TPCC_EECRH_E56=1;TPCC_TPCC_EECRH_E57=1;TPCC_TPCC_EECRH_E58=1; TPCC_TPCC_EECRH_E59=1;TPCC_TPCC_EECRH_E60=1;TPCC_TPCC_EECRH_E61=1; TPCC_TPCC_EECRH_E62=1;TPCC_TPCC_EECRH_E63=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Disables DMA Channel 0 CSL_edma3DMAChannelDisable(hModule, 0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3DMAChannelEnable | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
Uint8 | dmaChannel | |||
) |
============================================================================
CSL_edma3DMAChannelEnable
Description
This API enables the specified DMA Channel.
Arguments
hModule Module Handle region Region (Shadow or Global) dmaChannel DMA Channel to be enabled.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_EESR_E0=1;TPCC_TPCC_EESR_E1=1;TPCC_TPCC_EESR_E2=1; TPCC_TPCC_EESR_E3=1;TPCC_TPCC_EESR_E4=1;TPCC_TPCC_EESR_E5=1; TPCC_TPCC_EESR_E6=1;TPCC_TPCC_EESR_E7=1;TPCC_TPCC_EESR_E8=1; TPCC_TPCC_EESR_E9=1;TPCC_TPCC_EESR_E10=1;TPCC_TPCC_EESR_E11=1; TPCC_TPCC_EESR_E12=1;TPCC_TPCC_EESR_E13=1;TPCC_TPCC_EESR_E14=1; TPCC_TPCC_EESR_E15=1;TPCC_TPCC_EESR_E16=1;TPCC_TPCC_EESR_E17=1; TPCC_TPCC_EESR_E18=1;TPCC_TPCC_EESR_E19=1;TPCC_TPCC_EESR_E20=1; TPCC_TPCC_EESR_E21=1;TPCC_TPCC_EESR_E22=1;TPCC_TPCC_EESR_E23=1; TPCC_TPCC_EESR_E24=1;TPCC_TPCC_EESR_E25=1;TPCC_TPCC_EESR_E26=1; TPCC_TPCC_EESR_E27=1;TPCC_TPCC_EESR_E28=1;TPCC_TPCC_EESR_E29=1; TPCC_TPCC_EESR_E30=1;TPCC_TPCC_EESR_E31=1;
TPCC_TPCC_EESRH_E32=1;TPCC_TPCC_EESRH_E33=1;TPCC_TPCC_EESRH_E34=1; TPCC_TPCC_EESRH_E35=1;TPCC_TPCC_EESRH_E36=1;TPCC_TPCC_EESRH_E37=1; TPCC_TPCC_EESRH_E38=1;TPCC_TPCC_EESRH_E39=1;TPCC_TPCC_EESRH_E40=1; TPCC_TPCC_EESRH_E41=1;TPCC_TPCC_EESRH_E42=1;TPCC_TPCC_EESRH_E43=1; TPCC_TPCC_EESRH_E44=1;TPCC_TPCC_EESRH_E45=1;TPCC_TPCC_EESRH_E46=1; TPCC_TPCC_EESRH_E47=1;TPCC_TPCC_EESRH_E48=1;TPCC_TPCC_EESRH_E49=1; TPCC_TPCC_EESRH_E50=1;TPCC_TPCC_EESRH_E51=1;TPCC_TPCC_EESRH_E52=1; TPCC_TPCC_EESRH_E53=1;TPCC_TPCC_EESRH_E54=1;TPCC_TPCC_EESRH_E55=1; TPCC_TPCC_EESRH_E56=1;TPCC_TPCC_EESRH_E57=1;TPCC_TPCC_EESRH_E58=1; TPCC_TPCC_EESRH_E59=1;TPCC_TPCC_EESRH_E60=1;TPCC_TPCC_EESRH_E61=1; TPCC_TPCC_EESRH_E62=1;TPCC_TPCC_EESRH_E63=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Enables DMA Channel 0 for the global region. CSL_edma3DMAChannelEnable(hModule, CSL_EDMA3_REGION_GLOBAL, 0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3DmaRegionAccessDisable | ( | CSL_Edma3Handle | hModule, | |
Int | edmaRegion, | |||
CSL_BitMask32 | drae, | |||
CSL_BitMask32 | draeh | |||
) |
============================================================================
CSL_edma3DmaRegionAccessDisable
Description
This API disables read/write access to the shadow regions for the specific DMA channels.
Arguments
hModule Module Handle edmaRegion Shadow Region access Region bits to be programmed drae Bitmask to be disabled in DRAE draeh Bitmask to be disabled in DRAEH
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_DRA_DRAE_E0=0;TPCC_TPCC_DRA_DRAE_E1=0;TPCC_TPCC_DRA_DRAE_E2=0; TPCC_TPCC_DRA_DRAE_E3=0;TPCC_TPCC_DRA_DRAE_E4=0;TPCC_TPCC_DRA_DRAE_E5=0; TPCC_TPCC_DRA_DRAE_E6=0;TPCC_TPCC_DRA_DRAE_E7=0;TPCC_TPCC_DRA_DRAE_E8=0; TPCC_TPCC_DRA_DRAE_E9=0;TPCC_TPCC_DRA_DRAE_E10=0;TPCC_TPCC_DRA_DRAE_E11=0; TPCC_TPCC_DRA_DRAE_E12=0;TPCC_TPCC_DRA_DRAE_E13=0;TPCC_TPCC_DRA_DRAE_E14=0; TPCC_TPCC_DRA_DRAE_E15=0;TPCC_TPCC_DRA_DRAE_E16=0;TPCC_TPCC_DRA_DRAE_E17=0; TPCC_TPCC_DRA_DRAE_E18=0;TPCC_TPCC_DRA_DRAE_E19=0;TPCC_TPCC_DRA_DRAE_E20=0; TPCC_TPCC_DRA_DRAE_E21=0;TPCC_TPCC_DRA_DRAE_E22=0;TPCC_TPCC_DRA_DRAE_E23=0; TPCC_TPCC_DRA_DRAE_E24=0;TPCC_TPCC_DRA_DRAE_E25=0;TPCC_TPCC_DRA_DRAE_E26=0; TPCC_TPCC_DRA_DRAE_E27=0;TPCC_TPCC_DRA_DRAE_E28=0;TPCC_TPCC_DRA_DRAE_E29=0; TPCC_TPCC_DRA_DRAE_E30=0;TPCC_TPCC_DRA_DRAE_E31=0;
TPCC_TPCC_DRA_DRAEH_E32=0;TPCC_TPCC_DRA_DRAEH_E33=0;TPCC_TPCC_DRA_DRAEH_E34=0; TPCC_TPCC_DRA_DRAEH_E35=0;TPCC_TPCC_DRA_DRAEH_E36=0;TPCC_TPCC_DRA_DRAEH_E37=0; TPCC_TPCC_DRA_DRAEH_E38=0;TPCC_TPCC_DRA_DRAEH_E39=0;TPCC_TPCC_DRA_DRAEH_E40=0; TPCC_TPCC_DRA_DRAEH_E41=0;TPCC_TPCC_DRA_DRAEH_E42=0;TPCC_TPCC_DRA_DRAEH_E43=0; TPCC_TPCC_DRA_DRAEH_E44=0;TPCC_TPCC_DRA_DRAEH_E45=0;TPCC_TPCC_DRA_DRAEH_E46=0; TPCC_TPCC_DRA_DRAEH_E47=0;TPCC_TPCC_DRA_DRAEH_E48=0;TPCC_TPCC_DRA_DRAEH_E49=0; TPCC_TPCC_DRA_DRAEH_E50=0;TPCC_TPCC_DRA_DRAEH_E51=0;TPCC_TPCC_DRA_DRAEH_E52=0; TPCC_TPCC_DRA_DRAEH_E53=0;TPCC_TPCC_DRA_DRAEH_E54=0;TPCC_TPCC_DRA_DRAEH_E55=0; TPCC_TPCC_DRA_DRAEH_E56=0;TPCC_TPCC_DRA_DRAEH_E57=0;TPCC_TPCC_DRA_DRAEH_E58=0; TPCC_TPCC_DRA_DRAEH_E59=0;TPCC_TPCC_DRA_DRAEH_E60=0;TPCC_TPCC_DRA_DRAEH_E61=0; TPCC_TPCC_DRA_DRAEH_E62=0;TPCC_TPCC_DRA_DRAEH_E63=0;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Disable read/write access in Region 0 for DMA Channel 0 to 7 CSL_edma3DmaRegionAccessDisable(hModule, 0, 0x000000FF, 0x0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3DmaRegionAccessEnable | ( | CSL_Edma3Handle | hModule, | |
Int | edmaRegion, | |||
CSL_BitMask32 | drae, | |||
CSL_BitMask32 | draeh | |||
) |
============================================================================
CSL_edma3DmaRegionAccessEnable
Description
This API enables read/write access to the shadow regions for the specific DMA channels.
Arguments
hModule Module Handle edmaRegion Shadow Region access Region bits to be programmed drae Bitmask to be enabled in DRAE draeh Bitmask to be enabled in DRAEH
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_DRA_DRAE_E0=1;TPCC_TPCC_DRA_DRAE_E1=1;TPCC_TPCC_DRA_DRAE_E2=1; TPCC_TPCC_DRA_DRAE_E3=1;TPCC_TPCC_DRA_DRAE_E4=1;TPCC_TPCC_DRA_DRAE_E5=1; TPCC_TPCC_DRA_DRAE_E6=1;TPCC_TPCC_DRA_DRAE_E7=1;TPCC_TPCC_DRA_DRAE_E8=1; TPCC_TPCC_DRA_DRAE_E9=1;TPCC_TPCC_DRA_DRAE_E10=1;TPCC_TPCC_DRA_DRAE_E11=1; TPCC_TPCC_DRA_DRAE_E12=1;TPCC_TPCC_DRA_DRAE_E13=1;TPCC_TPCC_DRA_DRAE_E14=1; TPCC_TPCC_DRA_DRAE_E15=1;TPCC_TPCC_DRA_DRAE_E16=1;TPCC_TPCC_DRA_DRAE_E17=1; TPCC_TPCC_DRA_DRAE_E18=1;TPCC_TPCC_DRA_DRAE_E19=1;TPCC_TPCC_DRA_DRAE_E20=1; TPCC_TPCC_DRA_DRAE_E21=1;TPCC_TPCC_DRA_DRAE_E22=1;TPCC_TPCC_DRA_DRAE_E23=1; TPCC_TPCC_DRA_DRAE_E24=1;TPCC_TPCC_DRA_DRAE_E25=1;TPCC_TPCC_DRA_DRAE_E26=1; TPCC_TPCC_DRA_DRAE_E27=1;TPCC_TPCC_DRA_DRAE_E28=1;TPCC_TPCC_DRA_DRAE_E29=1; TPCC_TPCC_DRA_DRAE_E30=1;TPCC_TPCC_DRA_DRAE_E31=1;
TPCC_TPCC_DRA_DRAEH_E32=1;TPCC_TPCC_DRA_DRAEH_E33=1;TPCC_TPCC_DRA_DRAEH_E34=1; TPCC_TPCC_DRA_DRAEH_E35=1;TPCC_TPCC_DRA_DRAEH_E36=1;TPCC_TPCC_DRA_DRAEH_E37=1; TPCC_TPCC_DRA_DRAEH_E38=1;TPCC_TPCC_DRA_DRAEH_E39=1;TPCC_TPCC_DRA_DRAEH_E40=1; TPCC_TPCC_DRA_DRAEH_E41=1;TPCC_TPCC_DRA_DRAEH_E42=1;TPCC_TPCC_DRA_DRAEH_E43=1; TPCC_TPCC_DRA_DRAEH_E44=1;TPCC_TPCC_DRA_DRAEH_E45=1;TPCC_TPCC_DRA_DRAEH_E46=1; TPCC_TPCC_DRA_DRAEH_E47=1;TPCC_TPCC_DRA_DRAEH_E48=1;TPCC_TPCC_DRA_DRAEH_E49=1; TPCC_TPCC_DRA_DRAEH_E50=1;TPCC_TPCC_DRA_DRAEH_E51=1;TPCC_TPCC_DRA_DRAEH_E52=1; TPCC_TPCC_DRA_DRAEH_E53=1;TPCC_TPCC_DRA_DRAEH_E54=1;TPCC_TPCC_DRA_DRAEH_E55=1; TPCC_TPCC_DRA_DRAEH_E56=1;TPCC_TPCC_DRA_DRAEH_E57=1;TPCC_TPCC_DRA_DRAEH_E58=1; TPCC_TPCC_DRA_DRAEH_E59=1;TPCC_TPCC_DRA_DRAEH_E60=1;TPCC_TPCC_DRA_DRAEH_E61=1; TPCC_TPCC_DRA_DRAEH_E62=1;TPCC_TPCC_DRA_DRAEH_E63=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Enable read/write access in Region 0 for DMA Channel 0 to 7 CSL_edma3DmaRegionAccessEnable(hModule, 0, 0x000000FF, 0x0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3ErrorEval | ( | CSL_Edma3Handle | hModule | ) |
============================================================================
CSL_edma3ErrorEval
Description
This API enables enables evaluation of errros for the specified view/shadow region.Sets EVAL bit of the EEVAL register in the Global register space
Arguments
hModule Module Handle
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_EEVAL_EVAL=1
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Set the Error Interrupt Evaluation CSL_edma3ErrorEval(hModule); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3EventQueueThresholdSet | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue, | |||
Uint8 | threshold | |||
) |
============================================================================
CSL_edma3EventQueueThresholdSet
Description
The function configures the queue threshold.
Arguments
hModule Module Handle eventQueue Event queue for which the threshold is configured threshold Target threshold value.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_QWMTHRA_Q0;TPCC_TPCC_QWMTHRA_Q1;TPCC_TPCC_QWMTHRA_Q2; TPCC_TPCC_QWMTHRA_Q3;
TPCC_TPCC_QWMTHRB_Q4;TPCC_TPCC_QWMTHRB_Q1;TPCC_TPCC_QWMTHRB_Q2; TPCC_TPCC_QWMTHRB_Q3
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Set the Queue threshold for Event Queue 0 to be 9 CSL_edma3EventQueueThresholdSet(hModule, 0, 9); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3EventsMissedClear | ( | CSL_Edma3Handle | hModule, | |
CSL_BitMask32 | missedLo, | |||
CSL_BitMask32 | missedHi, | |||
CSL_BitMask32 | missedQdma | |||
) |
============================================================================
CSL_edma3EventMissedClear
Description
Clear the Event missed errors
Arguments
hModule Module Handle missedLo Lower 32 of of the Event Missed register needing to be cleared (This is the same value as EMR) missedHi Upper 32 of of the Event Missed register needing to be cleared (This is the same value as EMRH) missedQdma Bit mask of Qdma events missed needing to be cleared
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
Clears all the missed events
Writes
TPCC_TPCC_EMCR,TPCC_TPCC_EMCRH,TPCC_TPCC_QEMCR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 missedLo, missedHi, missedQdma; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get the missed events CSL_edma3GetEventMissed(hModule, &missedEdma, &missedEdmaHi, &missedQdma); ... // Clear the error CSL_edma3EventMissedClear(hModule,missedLo, missedHi,qdmamissed); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetActivityStatus | ( | CSL_Edma3Handle | hModule, | |
CSL_Edma3ActivityStat * | activityStat | |||
) |
============================================================================
CSL_edma3GetActivityStatus
Description
Obtains the Channel Controller Activity Status
Arguments
hModule Module Handle activityStat Activity Status populated by this API.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_CCSTAT_EVTACTV,TPCC_TPCC_CCSTAT_QEVTACTV,TPCC_TPCC_CCSTAT_TRACTV, TPCC_TPCC_CCSTAT_ACTV,TPCC_TPCC_CCSTAT_COMP_ACTV
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3ActivityStat activityStat; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get the CC activity status. CSL_edma3GetActivityStatus(hModule,&activityStat); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetControllerError | ( | CSL_Edma3Handle | hModule, | |
CSL_Edma3CtrlErrStat * | ccStat | |||
) |
============================================================================
CSL_edma3GetControllerError
Description
The function gets the status of the controller error.
Arguments
hModule Module Handle ccStat Controller Error populated by this API
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_CCERR_QTHRXD0;TPCC_TPCC_CCERR_QTHRXD1;TPCC_TPCC_CCERR_QTHRXD2; TPCC_TPCC_CCERR_QTHRXD3;TPCC_TPCC_CCERR_QTHRXD4;TPCC_TPCC_CCERR_QTHRXD5; TPCC_TPCC_CCERR_QTHRXD6;TPCC_TPCC_CCERR_QTHRXD7, TPCC_TPCC_CCERR_TCCERR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3CtrlErrStat ccError; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get Controller Error status = CSL_edma3GetControllerError(hModule,&ccError); ...
===========================================================================
CSL_IDEF_INLINE Uint8 CSL_edma3GetDMAChannelToEventQueueMapping | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel | |||
) |
============================================================================
CSL_edma3GetDMAChannelToEventQueueMapping
Description
The function gets the mapping of the DMA Channel to the Event Queue
Arguments
hModule Module Handle dmaChannel DMA Channel for which the mapping is to be retreived.
Return Value
Event Queue to which the DMA channel is mapped to
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_DMAQNUM_E0;TPCC_TPCC_DMAQNUM_E1;TPCC_TPCC_DMAQNUM_E2; TPCC_TPCC_DMAQNUM_E3;TPCC_TPCC_DMAQNUM_E4;TPCC_TPCC_DMAQNUM_E5; TPCC_TPCC_DMAQNUM_E6;TPCC_TPCC_DMAQNUM_E7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 eventQueue; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Get the Event Queue mapping of DMA Channel 1 eventQueue = CSL_edma3GetDMAChannelToEventQueueMapping(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE Uint16 CSL_edma3GetDMAChannelToParamBlockMapping | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel | |||
) |
============================================================================
CSL_edma3GetDMAChannelToParamBlockMapping
Description
The function gets the PARAM Entry ID to which a specific DMA Channel is mapped.
Arguments
hModule Module Handle dmaChannel DMA Channel Number whose mapping is to be found.
Return Value
Paramater ID to which the specific DMA Channel is mapped to.
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_DCHMAP_PAENTRY
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint16 paramId; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Get the mapping information for DMA channel 1. paramId = CSL_edma3GetDMAChannelToParamBlockMapping(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetDMASecondaryEvents | ( | CSL_Edma3Handle | hModule, | |
CSL_BitMask32 * | secEventLo, | |||
CSL_BitMask32 * | secEventHi | |||
) |
============================================================================
CSL_edma3GetDMASecondaryEvents
Description
This API gets the DMA secondary events
Arguments
hModule Module Handle secEventLo Lower order 32 bits of secondary events populated by the API secEventHi Higher order 32 bits of secondary events populated by the API
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_SER,TPCC_TPCC_SERH
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 secEventLo; CSL_BitMask32 secEventHi; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Get the DMA Secondary Events. CSL_edma3GetDMASecondaryEvents(hModule, &secEventLo, &secEventHi); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetEventMissed | ( | CSL_Edma3Handle | hModule, | |
CSL_BitMask32 * | missedLo, | |||
CSL_BitMask32 * | missedHi, | |||
CSL_BitMask32 * | missedQdma | |||
) |
============================================================================
CSL_edma3GetEventMissed
Description
Queries all the events missed.Since there may be upto 64 EDMA channels + upto 8 QDMA channels,this points to an array of 3, 32 bit elements.Gets the status of the missed events.
Arguments
hModule Module Handle missedLo missed [0] - holds status from EMR missedHi missed [1] - holds status from EMRH missedQdma missed [2] - holds status from QEMR
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_EMR,TPCC_TPCC_EMRH,TPCC_TPCC_QEMR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 missedLo, missedHi, missedQdma; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get the missed events CSL_edma3GetEventMissed(hModule, &missedEdma, &missedEdmaHi, &missedQdma); ...
===========================================================================
CSL_IDEF_INLINE Uint8 CSL_edma3GetEventQueuePriority | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue | |||
) |
============================================================================
CSL_edma3GetEventQueuePriority
Description
The function gets the priority of the specific event queue.
Arguments
hModule Module Handle eventQueue Event Queue whose priority is to be retrieved.
Return Value
Priority to which the Event Queue is mapped to.
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
Event Queue is configured to the specific priority.
Reads
TPCC_TPCC_QUEPRI_PRIQ0;TPCC_TPCC_QUEPRI_PRIQ1;TPCC_TPCC_QUEPRI_PRIQ2; TPCC_TPCC_QUEPRI_PRIQ3;TPCC_TPCC_QUEPRI_PRIQ4;TPCC_TPCC_QUEPRI_PRIQ5; TPCC_TPCC_QUEPRI_PRIQ6;TPCC_TPCC_QUEPRI_PRIQ7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 priority; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Get the priority of Event Queue 2. priority = CSL_edma3GetEventQueuePriority(hModule, 2); ...
===========================================================================
CSL_IDEF_INLINE Uint8 CSL_edma3GetEventQueueToTCMapping | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue | |||
) |
============================================================================
CSL_edma3GetEventQueueToTCMapping
Description
The function gets the TC mapping for the specific event queue.
Arguments
hModule Module Handle eventQueue Event Queue which for which the mapping is needed.
Return Value
TC Number to which the event queue is mapped to
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
Event Queue is mapped to the specific TC
Reads
TPCC_TPCC_QUETCMAP_TCNUMQ0;TPCC_TPCC_QUETCMAP_TCNUMQ1;TPCC_TPCC_QUETCMAP_TCNUMQ2; TPCC_TPCC_QUETCMAP_TCNUMQ3;TPCC_TPCC_QUETCMAP_TCNUMQ4;TPCC_TPCC_QUETCMAP_TCNUMQ5; TPCC_TPCC_QUETCMAP_TCNUMQ6;TPCC_TPCC_QUETCMAP_TCNUMQ7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 tcNum; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Get the TC mapping for Event Queue 1 tcNum = CSL_edma3GetEventQueueToTCMapping(hModule, 1, 0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetHiPendingInterrupts | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 * | intrHi | |||
) |
============================================================================
CSL_edma3GetHiPendingInterrupts
Description
The API gets a bitmask of all high pending interrupts.
Arguments
hModule Module Handle region Region (Shadown Region or Global) intrHi Status 32-63 of the interrupts
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_IPRH
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 edmaIntrHi; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get all the high pending interrupts for the global region. CSL_edma3GetHiPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, &edmaIntrHi); ...
===========================================================================
CSL_Status CSL_edma3GetHwChannelSetupParam | ( | CSL_Edma3ChannelHandle | hEdma, | |
Uint16 * | paramNum | |||
) |
============================================================================
CSL_edma3GetHwChannelSetupParam
Description
The function gets the DMA/QDMA Channel to PARAM Entry Mapping.
Arguments
hEdma Channel Handle paramNum Pointer to parameter entry to which the channel is mapped.
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameters passed is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before CSL_edma3GetHwChannelSetupParam() can be invoked.
Post Condition
None
Reads
TPCC_TPCC_DCHMAP_PAENTRY;
TPCC_TPCC_QCHMAP_PAENTRY
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Status status; Uint16 paramNum; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, 0, NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 0; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ... // Get the parameter entry number to which a channel is mapped to CSL_edma3GetHwChannelSetupParam(hChannel,¶mNum); ...
=============================================================================
CSL_Status CSL_edma3GetHwChannelSetupQue | ( | CSL_Edma3ChannelHandle | hEdma, | |
CSL_Edma3Que * | evtQue | |||
) |
============================================================================
CSL_edma3GetHwChannelSetupQue
Description
The function gets the event queue to which the specific DMA/QDMA channel is mapped.
Arguments
hEdma Channel Handle evtQue Event Queue to which the DMA/QDMA channel is mapped.
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameters passed is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before CSL_edma3GetHwChannelSetupQue() can be called.
Post Condition
None
Reads
TPCC_TPCC_QDMAQNUM_E0;TPCC_TPCC_QDMAQNUM_E1;TPCC_TPCC_QDMAQNUM_E2; TPCC_TPCC_QDMAQNUM_E3;TPCC_TPCC_QDMAQNUM_E4;TPCC_TPCC_QDMAQNUM_E5; TPCC_TPCC_QDMAQNUM_E6;TPCC_TPCC_QDMAQNUM_E7;
TPCC_TPCC_DMAQNUM_E0;TPCC_TPCC_DMAQNUM_E1;TPCC_TPCC_DMAQNUM_E2; TPCC_TPCC_DMAQNUM_E3;TPCC_TPCC_DMAQNUM_E4;TPCC_TPCC_DMAQNUM_E5; TPCC_TPCC_DMAQNUM_E6;TPCC_TPCC_DMAQNUM_E7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Status status; CSL_Edma3Que evtQue; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, 0, NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 0; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ... // Get the trigger word programmed for the channel CSL_edma3GetHwChannelSetupQue(hChannel, &evtQue); ...
=============================================================================
CSL_Status CSL_edma3GetHwChannelSetupTriggerWord | ( | CSL_Edma3ChannelHandle | hEdma, | |
Uint8 * | triggerWord | |||
) |
============================================================================
CSL_edma3GetHwChannelSetupTriggerWord
Description
The function gets the Trigger word for a specific QDMA Channel.
Arguments
hEdma Channel Handle (Only QDMA Channels) triggerWord Pointer to Trigger word populated by this API.
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameters passed is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before CSL_edma3GetHwChannelSetupTriggerWord() can be called.
Post Condition
None
Reads
TPCC_TPCC_QCHMAP0_TRWORD
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Status status; Uint8 triggerWord; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, 0, NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 0; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ... // Get the trigger word programmed for the channel CSL_edma3GetHwChannelSetupTriggerWord(hChannel,&triggerWord); ...
=============================================================================
CSL_Status CSL_edma3GetHwChannelStatus | ( | CSL_Edma3ChannelHandle | hEdma, | |
CSL_Edma3HwChannelStatusQuery | myQuery, | |||
void * | response | |||
) |
============================================================================
CSL_edma3GetHwChannelStatus
Description
The function is to used to get the status of entities specific to an EDMA Channel. The channel specific entity to be queried is specified in the argument.
Arguments
hEdma Channel Handle myQuery Query to be performed response Pointer to buffer to return the data requested by the query passed
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVQUERY (The query passed is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before this API can be invoked.If a Shadow region is used then care of the DRAE settings must be taken
Post Condition
None
Reads
TPCC_TPCC_ER_E0;TPCC_TPCC_ER_E1;TPCC_TPCC_ER_E2;TPCC_TPCC_ER_E3; TPCC_TPCC_ER_E4;TPCC_TPCC_ER_E5;TPCC_TPCC_ER_E6;TPCC_TPCC_ER_E7; TPCC_TPCC_ER_E8;TPCC_TPCC_ER_E9;TPCC_TPCC_ER_E10;TPCC_TPCC_ER_E11; TPCC_TPCC_ER_E12;TPCC_TPCC_ER_E13;TPCC_TPCC_ER_E14;TPCC_TPCC_ER_E15; TPCC_TPCC_ER_E16;TPCC_TPCC_ER_E17;TPCC_TPCC_ER_E18;TPCC_TPCC_ER_E19; TPCC_TPCC_ER_E20;TPCC_TPCC_ER_E21;TPCC_TPCC_ER_E22;TPCC_TPCC_ER_E23; TPCC_TPCC_ER_E24;TPCC_TPCC_ER_E25;TPCC_TPCC_ER_E26;TPCC_TPCC_ER_E27; TPCC_TPCC_ER_E28;TPCC_TPCC_ER_E29;TPCC_TPCC_ER_E30;TPCC_TPCC_ER_E31;
TPCC_TPCC_ERH_E32;TPCC_TPCC_ERH_E33;TPCC_TPCC_ERH_E34;TPCC_TPCC_ERH_E35; TPCC_TPCC_ERH_E36;TPCC_TPCC_ERH_E37;TPCC_TPCC_ERH_E38;TPCC_TPCC_ERH_E39; TPCC_TPCC_ERH_E40;TPCC_TPCC_ERH_E41;TPCC_TPCC_ERH_E42;TPCC_TPCC_ERH_E43; TPCC_TPCC_ERH_E44;TPCC_TPCC_ERH_E45;TPCC_TPCC_ERH_E46;TPCC_TPCC_ERH_E47; TPCC_TPCC_ERH_E48;TPCC_TPCC_ERH_E49;TPCC_TPCC_ERH_E50;TPCC_TPCC_ERH_E51; TPCC_TPCC_ERH_E52;TPCC_TPCC_ERH_E53;TPCC_TPCC_ERH_E54;TPCC_TPCC_ERH_E55; TPCC_TPCC_ERH_E56;TPCC_TPCC_ERH_E57;TPCC_TPCC_ERH_E58;TPCC_TPCC_ERH_E59; TPCC_TPCC_ERH_E60;TPCC_TPCC_ERH_E61;TPCC_TPCC_ERH_E62;TPCC_TPCC_ERH_E63;
TPCC_TPCC_QER_QER0;TPCC_TPCC_QER_QER1;TPCC_TPCC_QER_QER2;TPCC_TPCC_QER_QER3; TPCC_TPCC_QER_QER4;TPCC_TPCC_QER_QER5;TPCC_TPCC_QER_QER6;TPCC_TPCC_QER_QER7;
TPCC_TPCC_EMR_EMR0;TPCC_TPCC_EMR_EMR1;TPCC_TPCC_EMR_EMR2; TPCC_TPCC_EMR_EMR3;TPCC_TPCC_EMR_EMR4;TPCC_TPCC_EMR_EMR5; TPCC_TPCC_EMR_EMR6;TPCC_TPCC_EMR_EMR7;TPCC_TPCC_EMR_EMR8; TPCC_TPCC_EMR_EMR9;TPCC_TPCC_EMR_EMR10;TPCC_TPCC_EMR_EMR11; TPCC_TPCC_EMR_EMR12;TPCC_TPCC_EMR_EMR13;TPCC_TPCC_EMR_EMR14; TPCC_TPCC_EMR_EMR15;TPCC_TPCC_EMR_EMR16;TPCC_TPCC_EMR_EMR17; TPCC_TPCC_EMR_EMR18;TPCC_TPCC_EMR_EMR19;TPCC_TPCC_EMR_EMR20; TPCC_TPCC_EMR_EMR21;TPCC_TPCC_EMR_EMR22;TPCC_TPCC_EMR_EMR23; TPCC_TPCC_EMR_EMR24;TPCC_TPCC_EMR_EMR25;TPCC_TPCC_EMR_EMR26; TPCC_TPCC_EMR_EMR27;TPCC_TPCC_EMR_EMR28;TPCC_TPCC_EMR_EMR29; TPCC_TPCC_EMR_EMR30;TPCC_TPCC_EMR_EMR31;
TPCC_TPCC_EMRH_EMR32;TPCC_TPCC_EMRH_EMR33;TPCC_TPCC_EMRH_EMR34; TPCC_TPCC_EMRH_EMR35;TPCC_TPCC_EMRH_EMR36;TPCC_TPCC_EMRH_EMR37; TPCC_TPCC_EMRH_EMR38;TPCC_TPCC_EMRH_EMR39;TPCC_TPCC_EMRH_EMR40; TPCC_TPCC_EMRH_EMR41;TPCC_TPCC_EMRH_EMR42;TPCC_TPCC_EMRH_EMR43; TPCC_TPCC_EMRH_EMR44;TPCC_TPCC_EMRH_EMR45;TPCC_TPCC_EMRH_EMR46; TPCC_TPCC_EMRH_EMR47;TPCC_TPCC_EMRH_EMR48;TPCC_TPCC_EMRH_EMR49; TPCC_TPCC_EMRH_EMR50;TPCC_TPCC_EMRH_EMR51;TPCC_TPCC_EMRH_EMR52; TPCC_TPCC_EMRH_EMR53;TPCC_TPCC_EMRH_EMR54;TPCC_TPCC_EMRH_EMR55; TPCC_TPCC_EMRH_EMR56;TPCC_TPCC_EMRH_EMR57;TPCC_TPCC_EMRH_EMR58; TPCC_TPCC_EMRH_EMR59;TPCC_TPCC_EMRH_EMR60;TPCC_TPCC_EMRH_EMR61; TPCC_TPCC_EMRH_EMR62;TPCC_TPCC_EMRH_EMR63,
TPCC_TPCC_SER_SER0;TPCC_TPCC_SER_SER1;TPCC_TPCC_SER_SER2; TPCC_TPCC_SER_SER3;TPCC_TPCC_SER_SER4;TPCC_TPCC_SER_SER5; TPCC_TPCC_SER_SER6;TPCC_TPCC_SER_SER7;TPCC_TPCC_SER_SER8; TPCC_TPCC_SER_SER9;TPCC_TPCC_SER_SER10;TPCC_TPCC_SER_SER11; TPCC_TPCC_SER_SER12;TPCC_TPCC_SER_SER13;TPCC_TPCC_SER_SER14; TPCC_TPCC_SER_SER15;TPCC_TPCC_SER_SER16;TPCC_TPCC_SER_SER17; TPCC_TPCC_SER_SER18;TPCC_TPCC_SER_SER19;TPCC_TPCC_SER_SER20; TPCC_TPCC_SER_SER21;TPCC_TPCC_SER_SER22;TPCC_TPCC_SER_SER23; TPCC_TPCC_SER_SER24;TPCC_TPCC_SER_SER25;TPCC_TPCC_SER_SER26; TPCC_TPCC_SER_SER27;TPCC_TPCC_SER_SER28;TPCC_TPCC_SER_SER29; TPCC_TPCC_SER_SER30;TPCC_TPCC_SER_SER31;
TPCC_TPCC_SERH_SER32;TPCC_TPCC_SERH_SER33;TPCC_TPCC_SERH_SER34; TPCC_TPCC_SERH_SER35;TPCC_TPCC_SERH_SER36;TPCC_TPCC_SERH_SER37; TPCC_TPCC_SERH_SER38;TPCC_TPCC_SERH_SER39;TPCC_TPCC_SERH_SER40; TPCC_TPCC_SERH_SER41;TPCC_TPCC_SERH_SER42;TPCC_TPCC_SERH_SER43; TPCC_TPCC_SERH_SER44;TPCC_TPCC_SERH_SER45;TPCC_TPCC_SERH_SER46; TPCC_TPCC_SERH_SER47;TPCC_TPCC_SERH_SER48;TPCC_TPCC_SERH_SER49; TPCC_TPCC_SERH_SER50;TPCC_TPCC_SERH_SER51;TPCC_TPCC_SERH_SER52; TPCC_TPCC_SERH_SER53;TPCC_TPCC_SERH_SER54;TPCC_TPCC_SERH_SER55; TPCC_TPCC_SERH_SER56;TPCC_TPCC_SERH_SER57;TPCC_TPCC_SERH_SER58; TPCC_TPCC_SERH_SER59;TPCC_TPCC_SERH_SER60;TPCC_TPCC_SERH_SER61; TPCC_TPCC_SERH_SER62;TPCC_TPCC_SERH_SER63;
TPCC_TPCC_QEMR_QEMR0;TPCC_TPCC_QEMR_QEMR1;TPCC_TPCC_QEMR_QEMR2; TPCC_TPCC_QEMR_QEMR3;TPCC_TPCC_QEMR_QEMR4;TPCC_TPCC_QEMR_QEMR5; TPCC_TPCC_QEMR_QEMR6;TPCC_TPCC_QEMR_QEMR7,
TPCC_TPCC_QSER_QSER0;TPCC_TPCC_QSER_QSER1;TPCC_TPCC_QSER_QSER2; TPCC_TPCC_QSER_QSER3;TPCC_TPCC_QSER_QSER4;TPCC_TPCC_QSER_QSER5; TPCC_TPCC_QSER_QSER6;TPCC_TPCC_QSER_QSER7;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Status status; CSL_Edma3ChannelErr errStat; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj, 0, NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 0; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ... // Get the Channel 0 Error Status CSL_edma3GetHwChannelStatus(hChannel, CSL_EDMA3_QUERY_CHANNEL_ERR, &errStat); ...
=============================================================================
CSL_Status CSL_edma3GetHwSetup | ( | CSL_Edma3Handle | hMod, | |
CSL_Edma3HwSetup * | setup | |||
) |
============================================================================
CSL_edma3GetHwSetup
Description
The function gets the hardware setup for all DMA/QDMA Channels.
Arguments
hMod EDMA Handle setup Setup structure which is populated by this API.
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open() must be called successfully in that order before CSL_edma3GetHwSetup() can be called.
Post Condition
The hardware setup structure is populated with the hardware setup parameters
Reads
TPCC_TPCC_DCHMAP_PAENTRY,
TPCC_TPCC_DMAQNUM_E0;TPCC_TPCC_DMAQNUM_E1;TPCC_TPCC_DMAQNUM_E2; TPCC_TPCC_DMAQNUM_E3;TPCC_TPCC_DMAQNUM_E4;TPCC_TPCC_DMAQNUM_E5; TPCC_TPCC_DMAQNUM_E6;TPCC_TPCC_DMAQNUM_E7;
TPCC_TPCC_QCHMAP_PAENTRY,
TPCC_TPCC_QCHMAP_TRWORD,
TPCC_TPCC_QDMAQNUM_E0;TPCC_TPCC_QDMAQNUM_E1;TPCC_TPCC_QDMAQNUM_E2; TPCC_TPCC_QDMAQNUM_E3;TPCC_TPCC_QDMAQNUM_E4;TPCC_TPCC_QDMAQNUM_E5; TPCC_TPCC_QDMAQNUM_E6;TPCC_TPCC_QDMAQNUM_E7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3QueryInfo info; CSL_Edma3HwSetup setup; CSL_Edma3HwDmaChannelSetup dmahwSetup; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get DMA Channel Setup for all channels. setup.dmaChaSetup = &dmahwSetup[0]; setup.qdmaChaSetup = NULL; CSL_edma3GetHwSetup(hModule,&setup); ...
=============================================================================
CSL_Status CSL_edma3GetHwStatus | ( | CSL_Edma3Handle | hMod, | |
CSL_Edma3HwStatusQuery | myQuery, | |||
void * | response | |||
) |
============================================================================
CSL_edma3GetHwStatus
Description
The function gets the status of various entities in the EDMA module. The entity whose status needs to be retreived is specified in the query and the response is populated in the 'response'.
Arguments
hMod Edma module handle myQuery Query to be performed response Pointer to buffer to return the data requested by the query passed
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Error - CSL_ESYS_INVQUERY (The query is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open() must be called successfully in that order before this API can be invoked.argument type that can be void* casted & passed with a particular command refer to CSL_Edma3HwStatusQuery
Post Condition
None
Reads
TPCC_TPCC_CFG,TPCC_TPCC_PID;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3QueryInfo info; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Query Module Info CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INFO,&info); ...
=============================================================================
CSL_IDEF_INLINE void CSL_edma3GetInfo | ( | CSL_Edma3Handle | hModule, | |
CSL_Edma3QueryInfo * | response | |||
) |
============================================================================
CSL_edma3GetInfo
Description
The function gets the EDMA Channel Controller Configuration Information which includes reading the peripheral revision register and configuration register.
Arguments
hModule Module Handle response Output parameter populated with the configuration information.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_CFG,TPCC_TPCC_PID
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3QueryInfo info; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Get Module Info CSL_edma3GetInfo(hModule,&info); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetLoPendingInterrupts | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 * | intrLo | |||
) |
============================================================================
CSL_edma3GetLoPendingInterrupts
Description
The API gets a bitmask of all low pending interrupts.
Arguments
hModule Module Handle region Region (Shadown Region or Global) intrLo Status 0-31 of the interrupts
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_IPR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 edmaIntrLo; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get all low pending interrupts for the global region. CSL_edma3GetLoPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, &edmaIntrLo); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetMemoryFaultError | ( | CSL_Edma3Handle | hModule, | |
CSL_Edma3MemFaultStat * | memFault | |||
) |
============================================================================
CSL_edma3GetMemoryFaultError
Description
The function gets the Controllers memory fault error and the error attributes.
Arguments
hModule Module Handle memFault The structure is populated by this API.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_MPFAR_FADDR,TPCC_TPCC_MPFSR_FID, TPCC_TPCC_MPFSR_UXE,TPCC_TPCC_MPFSR_UWE,TPCC_TPCC_MPFSR_URE, TPCC_TPCC_MPFSR_SXE,TPCC_TPCC_MPFSR_SWE,TPCC_TPCC_MPFSR_SRE, TPCC_TPCC_MPFSR_SECE
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_Edma3MemFaultStat memFault; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get memory protection fault CSL_edma3GetMemoryFaultError(hModule, &memFault); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetMemoryProtectionAttrib | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 * | mppa | |||
) |
============================================================================
CSL_edma3GetMemoryProtectionAttrib
Description
The function gets the memory access/protection attributes of the specific region.
Arguments
hModule Module Handle region Region being queried. mppa Memory Access/Protection Attributes populated by this API
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_MPPAG;TPCC_TPCC_MPPA
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 mppa; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get memory protection attributes for the Global Region. CSL_edma3GetMemoryProtectionAttrib(hModule, -1, &mppa); ... // Get memory protection attributes for region 2 CSL_edma3GetMemoryProtectionAttrib(hModule, 2, &mppa); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetNumberValidEntries | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue, | |||
Uint8 * | numValidEntries | |||
) |
============================================================================
CSL_edma3GetNumberValidEntries
Description
The function gets the Number of valid entries for the specific event queue.
Arguments
hModule Module Handle eventQueue Event queue number for which the watermark is retreived. numValidEntries This is populated by the API to the number of valid entries
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QSTAT_NUMVAL
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 numVal; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Get the Number of valid entries in event queue 0. CSL_edma3GetNumberValidEntries(hModule, 0, &numVal); ...
===========================================================================
CSL_Edma3ParamHandle CSL_edma3GetParamHandle | ( | CSL_Edma3ChannelHandle | hEdma, | |
Int16 | paramNum, | |||
CSL_Status * | status | |||
) |
============================================================================
CSL_edma3GetParamHandle
Description
The function is used to get a specific PARAM Entry handle.
Arguments
hEdma Channel Handle paramNum Parameter entry number status Status of the function call
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Pre Condition
CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before this API can be invoked
Post Condition
None
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3ParamHandle hParamBasic; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Open DMA Channel 1. chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL; chAttr.chaNum = 1; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); if ((hChannel == NULL) || (status != CSL_SOK)) { printf ("Error: Unable to open EDMA Channel:%d\n", channelNum); return -1; } ... // Obtain a handle to PARAM Entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); ...
=============================================================================
CSL_IDEF_INLINE Uint8 CSL_edma3GetQDMAChannelToEventQueueMapping | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel | |||
) |
============================================================================
CSL_edma3GetQDMAChannelToEventQueueMapping
Description
The function gets the mapping of the QDMA Channel to the Event Queue
Arguments
hModule Module Handle qdmaChannel QDMA Channel for which the mapping is to be retreived.
Return Value
Event Queue to which the QDMA channel is mapped to
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QDMAQNUM_E0;TPCC_TPCC_QDMAQNUM_E1;TPCC_TPCC_QDMAQNUM_E2; TPCC_TPCC_QDMAQNUM_E3;TPCC_TPCC_QDMAQNUM_E4;TPCC_TPCC_QDMAQNUM_E5; TPCC_TPCC_QDMAQNUM_E6;TPCC_TPCC_QDMAQNUM_E7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 eventQueue; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Get the Event Queue mapping of QDMA Channel 1 eventQueue = CSL_edma3GetQDMAChannelToEventQueueMapping(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE Uint16 CSL_edma3GetQDMAChannelToParamBlockMapping | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel | |||
) |
============================================================================
CSL_edma3GetQDMAChannelToParamBlockMapping
Description
The function gets the PARAM Entry ID to which a specific QDMA Channel is mapped.
Arguments
hModule Module Handle qdmaChannel QDMA Channel Number whose mapping is to be found.
Return Value
Paramater ID to which the specific QDMA Channel is mapped to.
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QCHMAP_PAENTRY
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Get the mapping information for QDMA channel 1. paramId = CSL_edma3GetQDMAChannelMap(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetQDMASecondaryEvents | ( | CSL_Edma3Handle | hModule, | |
Uint32 * | qdmaSecEvent | |||
) |
============================================================================
CSL_edma3GetQDMASecondaryEvents
Description
This API reads the QDMA Secondary Event.
Arguments
hModule Module Handle qdmaSecEvent QDMA Secondary Event which is populated by this API
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QSER
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; Uint32 qdmaSecEvent; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Get the QDMA Secondary Event CSL_edma3GetQDMASecondaryEvents(hModule, &qdmaSecEvent); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetQDMATriggerWord | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel, | |||
Uint8 * | trword | |||
) |
============================================================================
CSL_edma3GetQDMATriggerWord
Description
The function gets the trigger word of the PaRAM Entry block.
Arguments
hModule Module Handle qdmaChannel QDMA Channel Number which is to be configured. trword Trigger Word to be retreived populated by this API.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
QDMA Channel is mapped to the specified PARAM Block.
Reads
TPCC_TPCC_QCHMAP_TRWORD
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 trWord; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Get the QDMA Channel 1 Trigger Word trWord = CSL_edma3SetQDMATriggerWord(hModule, 1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetStartPointer | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue, | |||
Uint8 * | startPtr | |||
) |
============================================================================
CSL_edma3GetStartPointer
Description
The function gets the Number of valid entries for the specific event queue.
Arguments
hModule Module Handle eventQueue Event queue number for which the watermark is retreived. startPtr This is populated by the API to the start pointer
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QSTAT_STRPTR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 startPtr; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Get the Number of valid entries in event queue 0. CSL_edma3GetStartPointer(hModule, 0, &startPtr); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetThresholdExceeded | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue, | |||
Bool * | thresholdExceeded | |||
) |
============================================================================
CSL_edma3GetThresholdExceeded
Description
The function gets the threshold exceeded flag for the specific event queue.
Arguments
hModule Module Handle eventQueue Event queue number for which the watermark is retreived. thresholdExceeded This is populated by the API to the threshold exceeded flag for the specific event queue.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QSTAT_THRXCD
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 thresholdExceeded; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Determine if the threshold has been exceeded or not for Queue 1 CSL_edma3GetThresholdExceeded(hModule, 1, &thresholdExceeded); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3GetWaterMark | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue, | |||
Uint8 * | waterMark | |||
) |
============================================================================
CSL_edma3GetWaterMark
Description
The function gets the Queue Watermark for the specific event queue.
Arguments
hModule Module Handle eventQueue Event queue number for which the watermark is retreived. waterMark This is populated by the API to the configured water mark
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QSTAT_WM
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Uint8 waterMark; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Get the Water Mark Queue for event queue 0 CSL_edma3GetWaterMark(hModule, 0, &waterMark); ...
===========================================================================
CSL_Status CSL_edma3HwChannelControl | ( | CSL_Edma3ChannelHandle | hCh, | |
CSL_Edma3HwChannelControlCmd | cmd, | |||
void * | cmdArg | |||
) |
============================================================================
CSL_edma3HwChannelControl
Description
This API is used to control the EDMA Channel. The function accepts a command as an argument on the type of operation which is to be performed on the specific channel.
Arguments
hCh Channel Handle cmd Command/Action to be performed on the channel handle. cmdArg Pointer to the argument specific to the command
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before this API can be invoked. If a Shadow region is used then care of the DRAE settings must be taken care of.
Post Condition
Edma registers are configured according to the command and the command arguements. The command determines which registers are modified.
Writes
TPCC_TPCC_QEESR_QEESR0=1;TPCC_TPCC_QEESR_QEESR1=1;TPCC_TPCC_QEESR_QEESR2=1; TPCC_TPCC_QEESR_QEESR3=1;TPCC_TPCC_QEESR_QEESR4=1;TPCC_TPCC_QEESR_QEESR5=1; TPCC_TPCC_QEESR_QEESR6=1;TPCC_TPCC_QEESR_QEESR7=1;
TPCC_TPCC_EESR_E0=1;TPCC_TPCC_EESR_E1=1;TPCC_TPCC_EESR_E2=1; TPCC_TPCC_EESR_E3=1;TPCC_TPCC_EESR_E4=1;TPCC_TPCC_EESR_E5=1; TPCC_TPCC_EESR_E6=1;TPCC_TPCC_EESR_E7=1;TPCC_TPCC_EESR_E8=1; TPCC_TPCC_EESR_E9=1;TPCC_TPCC_EESR_E10=1;TPCC_TPCC_EESR_E11=1; TPCC_TPCC_EESR_E12=1;TPCC_TPCC_EESR_E13=1;TPCC_TPCC_EESR_E14=1; TPCC_TPCC_EESR_E15=1;TPCC_TPCC_EESR_E16=1;TPCC_TPCC_EESR_E17=1; TPCC_TPCC_EESR_E18=1;TPCC_TPCC_EESR_E19=1;TPCC_TPCC_EESR_E20=1; TPCC_TPCC_EESR_E21=1;TPCC_TPCC_EESR_E22=1;TPCC_TPCC_EESR_E23=1; TPCC_TPCC_EESR_E24=1;TPCC_TPCC_EESR_E25=1;TPCC_TPCC_EESR_E26=1; TPCC_TPCC_EESR_E27=1;TPCC_TPCC_EESR_E28=1;TPCC_TPCC_EESR_E29=1; TPCC_TPCC_EESR_E30=1;TPCC_TPCC_EESR_E31=1;
TPCC_TPCC_EESRH_E32=1;TPCC_TPCC_EESRH_E33=1;TPCC_TPCC_EESRH_E34=1; TPCC_TPCC_EESRH_E35=1;TPCC_TPCC_EESRH_E36=1;TPCC_TPCC_EESRH_E37=1; TPCC_TPCC_EESRH_E38=1;TPCC_TPCC_EESRH_E39=1;TPCC_TPCC_EESRH_E40=1; TPCC_TPCC_EESRH_E41=1;TPCC_TPCC_EESRH_E42=1;TPCC_TPCC_EESRH_E43=1; TPCC_TPCC_EESRH_E44=1;TPCC_TPCC_EESRH_E45=1;TPCC_TPCC_EESRH_E46=1; TPCC_TPCC_EESRH_E47=1;TPCC_TPCC_EESRH_E48=1;TPCC_TPCC_EESRH_E49=1; TPCC_TPCC_EESRH_E50=1;TPCC_TPCC_EESRH_E51=1;TPCC_TPCC_EESRH_E52=1; TPCC_TPCC_EESRH_E53=1;TPCC_TPCC_EESRH_E54=1;TPCC_TPCC_EESRH_E55=1; TPCC_TPCC_EESRH_E56=1;TPCC_TPCC_EESRH_E57=1;TPCC_TPCC_EESRH_E58=1; TPCC_TPCC_EESRH_E59=1;TPCC_TPCC_EESRH_E60=1;TPCC_TPCC_EESRH_E61=1; TPCC_TPCC_EESRH_E62=1;TPCC_TPCC_EESRH_E63=1;
TPCC_TPCC_QEECR_QEECR0=1;TPCC_TPCC_QEECR_QEECR1=1;TPCC_TPCC_QEECR_QEECR2=1; TPCC_TPCC_QEECR_QEECR3=1;TPCC_TPCC_QEECR_QEECR4=1;TPCC_TPCC_QEECR_QEECR5=1; TPCC_TPCC_QEECR_QEECR6=1;TPCC_TPCC_QEECR_QEECR7=1;
TPCC_TPCC_EECR_E0=1;TPCC_TPCC_EECR_E1=1;TPCC_TPCC_EECR_E2=1; TPCC_TPCC_EECR_E3=1;TPCC_TPCC_EECR_E4=1;TPCC_TPCC_EECR_E5=1; TPCC_TPCC_EECR_E6=1;TPCC_TPCC_EECR_E7=1;TPCC_TPCC_EECR_E8=1; TPCC_TPCC_EECR_E9=1;TPCC_TPCC_EECR_E10=1;TPCC_TPCC_EECR_E11=1; TPCC_TPCC_EECR_E12=1;TPCC_TPCC_EECR_E13=1;TPCC_TPCC_EECR_E14=1; TPCC_TPCC_EECR_E15=1;TPCC_TPCC_EECR_E16=1;TPCC_TPCC_EECR_E17=1; TPCC_TPCC_EECR_E18=1;TPCC_TPCC_EECR_E19=1;TPCC_TPCC_EECR_E20=1; TPCC_TPCC_EECR_E21=1;TPCC_TPCC_EECR_E22=1;TPCC_TPCC_EECR_E23=1; TPCC_TPCC_EECR_E24=1;TPCC_TPCC_EECR_E25=1;TPCC_TPCC_EECR_E26=1; TPCC_TPCC_EECR_E27=1;TPCC_TPCC_EECR_E28=1;TPCC_TPCC_EECR_E29=1; TPCC_TPCC_EECR_E30=1;TPCC_TPCC_EECR_E31=1;
TPCC_TPCC_EECRH_E32=1;TPCC_TPCC_EECRH_E33=1;TPCC_TPCC_EECRH_E34=1; TPCC_TPCC_EECRH_E35=1;TPCC_TPCC_EECRH_E36=1;TPCC_TPCC_EECRH_E37=1; TPCC_TPCC_EECRH_E38=1;TPCC_TPCC_EECRH_E39=1;TPCC_TPCC_EECRH_E40=1; TPCC_TPCC_EECRH_E41=1;TPCC_TPCC_EECRH_E42=1;TPCC_TPCC_EECRH_E43=1; TPCC_TPCC_EECRH_E44=1;TPCC_TPCC_EECRH_E45=1;TPCC_TPCC_EECRH_E46=1; TPCC_TPCC_EECRH_E47=1;TPCC_TPCC_EECRH_E48=1;TPCC_TPCC_EECRH_E49=1; TPCC_TPCC_EECRH_E50=1;TPCC_TPCC_EECRH_E51=1;TPCC_TPCC_EECRH_E52=1; TPCC_TPCC_EECRH_E53=1;TPCC_TPCC_EECRH_E54=1;TPCC_TPCC_EECRH_E55=1; TPCC_TPCC_EECRH_E56=1;TPCC_TPCC_EECRH_E57=1;TPCC_TPCC_EECRH_E58=1; TPCC_TPCC_EECRH_E59=1;TPCC_TPCC_EECRH_E60=1;TPCC_TPCC_EECRH_E61=1; TPCC_TPCC_EECRH_E62=1;TPCC_TPCC_EECRH_E63=1;
TPCC_TPCC_ESR_E0=1;TPCC_TPCC_ESR_E1=1;TPCC_TPCC_ESR_E2=1;TPCC_TPCC_ESR_E3=1; TPCC_TPCC_ESR_E4=1;TPCC_TPCC_ESR_E5=1;TPCC_TPCC_ESR_E6=1;TPCC_TPCC_ESR_E7=1; TPCC_TPCC_ESR_E8=1;TPCC_TPCC_ESR_E9=1;TPCC_TPCC_ESR_E10=1;TPCC_TPCC_ESR_E11=1; TPCC_TPCC_ESR_E12=1;TPCC_TPCC_ESR_E13=1;TPCC_TPCC_ESR_E14=1;TPCC_TPCC_ESR_E15=1; TPCC_TPCC_ESR_E16=1;TPCC_TPCC_ESR_E17=1;TPCC_TPCC_ESR_E18=1;TPCC_TPCC_ESR_E19=1; TPCC_TPCC_ESR_E20=1;TPCC_TPCC_ESR_E21=1;TPCC_TPCC_ESR_E22=1;TPCC_TPCC_ESR_E23=1; TPCC_TPCC_ESR_E24=1;TPCC_TPCC_ESR_E25=1;TPCC_TPCC_ESR_E26=1;TPCC_TPCC_ESR_E27=1; TPCC_TPCC_ESR_E28=1;TPCC_TPCC_ESR_E29=1;TPCC_TPCC_ESR_E30=1;TPCC_TPCC_ESR_E31=1;
TPCC_TPCC_ESRH_E32=1;TPCC_TPCC_ESRH_E33=1;TPCC_TPCC_ESRH_E34=1;TPCC_TPCC_ESRH_E35=1; TPCC_TPCC_ESRH_E36=1;TPCC_TPCC_ESRH_E37=1;TPCC_TPCC_ESRH_E38=1;TPCC_TPCC_ESRH_E39=1; TPCC_TPCC_ESRH_E40=1;TPCC_TPCC_ESRH_E41=1;TPCC_TPCC_ESRH_E42=1;TPCC_TPCC_ESRH_E43=1; TPCC_TPCC_ESRH_E44=1;TPCC_TPCC_ESRH_E45=1;TPCC_TPCC_ESRH_E46=1;TPCC_TPCC_ESRH_E47=1; TPCC_TPCC_ESRH_E48=1;TPCC_TPCC_ESRH_E49=1;TPCC_TPCC_ESRH_E50=1;TPCC_TPCC_ESRH_E51=1; TPCC_TPCC_ESRH_E52=1;TPCC_TPCC_ESRH_E53=1;TPCC_TPCC_ESRH_E54=1;TPCC_TPCC_ESRH_E55=1; TPCC_TPCC_ESRH_E56=1;TPCC_TPCC_ESRH_E57=1;TPCC_TPCC_ESRH_E58=1;TPCC_TPCC_ESRH_E59=1; TPCC_TPCC_ESRH_E60=1;TPCC_TPCC_ESRH_E61=1;TPCC_TPCC_ESRH_E62=1;TPCC_TPCC_ESRH_E63=1;
TPCC_TPCC_ECR_E0=1;TPCC_TPCC_ECR_E1=1;TPCC_TPCC_ECR_E2=1;TPCC_TPCC_ECR_E3=1; TPCC_TPCC_ECR_E4=1;TPCC_TPCC_ECR_E5=1;TPCC_TPCC_ECR_E6=1;TPCC_TPCC_ECR_E7=1; TPCC_TPCC_ECR_E8=1;TPCC_TPCC_ECR_E9=1;TPCC_TPCC_ECR_E10=1;TPCC_TPCC_ECR_E11=1; TPCC_TPCC_ECR_E12=1;TPCC_TPCC_ECR_E13=1;TPCC_TPCC_ECR_E14=1;TPCC_TPCC_ECR_E15=1; TPCC_TPCC_ECR_E16=1;TPCC_TPCC_ECR_E17=1;TPCC_TPCC_ECR_E18=1;TPCC_TPCC_ECR_E19=1; TPCC_TPCC_ECR_E20=1;TPCC_TPCC_ECR_E21=1;TPCC_TPCC_ECR_E22=1;TPCC_TPCC_ECR_E23=1; TPCC_TPCC_ECR_E24=1;TPCC_TPCC_ECR_E25=1;TPCC_TPCC_ECR_E26=1;TPCC_TPCC_ECR_E27=1; TPCC_TPCC_ECR_E28=1;TPCC_TPCC_ECR_E29=1;TPCC_TPCC_ECR_E30=1;TPCC_TPCC_ECR_E31=1;
TPCC_TPCC_ECRH_E32=1;TPCC_TPCC_ECRH_E33=1;TPCC_TPCC_ECRH_E34=1;TPCC_TPCC_ECRH_E35=1; TPCC_TPCC_ECRH_E36=1;TPCC_TPCC_ECRH_E37=1;TPCC_TPCC_ECRH_E38=1;TPCC_TPCC_ECRH_E39=1; TPCC_TPCC_ECRH_E40=1;TPCC_TPCC_ECRH_E41=1;TPCC_TPCC_ECRH_E42=1;TPCC_TPCC_ECRH_E43=1; TPCC_TPCC_ECRH_E44=1;TPCC_TPCC_ECRH_E45=1;TPCC_TPCC_ECRH_E46=1;TPCC_TPCC_ECRH_E47=1; TPCC_TPCC_ECRH_E48=1;TPCC_TPCC_ECRH_E49=1;TPCC_TPCC_ECRH_E50=1;TPCC_TPCC_ECRH_E51=1; TPCC_TPCC_ECRH_E52=1;TPCC_TPCC_ECRH_E53=1;TPCC_TPCC_ECRH_E54=1;TPCC_TPCC_ECRH_E55=1; TPCC_TPCC_ECRH_E56=1;TPCC_TPCC_ECRH_E57=1;TPCC_TPCC_ECRH_E58=1;TPCC_TPCC_ECRH_E59=1; TPCC_TPCC_ECRH_E60=1;TPCC_TPCC_ECRH_E61=1;TPCC_TPCC_ECRH_E62=1;TPCC_TPCC_ECRH_E63=1;
TPCC_TPCC_EMCR_EMCR0;TPCC_TPCC_EMCR_EMCR1;TPCC_TPCC_EMCR_EMCR2; TPCC_TPCC_EMCR_EMCR3;TPCC_TPCC_EMCR_EMCR4;TPCC_TPCC_EMCR_EMCR5; TPCC_TPCC_EMCR_EMCR6;TPCC_TPCC_EMCR_EMCR7;TPCC_TPCC_EMCR_EMCR8; TPCC_TPCC_EMCR_EMCR9;TPCC_TPCC_EMCR_EMCR10;TPCC_TPCC_EMCR_EMCR11; TPCC_TPCC_EMCR_EMCR12;TPCC_TPCC_EMCR_EMCR13;TPCC_TPCC_EMCR_EMCR14; TPCC_TPCC_EMCR_EMCR15;TPCC_TPCC_EMCR_EMCR16;TPCC_TPCC_EMCR_EMCR17; TPCC_TPCC_EMCR_EMCR18;TPCC_TPCC_EMCR_EMCR19;TPCC_TPCC_EMCR_EMCR20; TPCC_TPCC_EMCR_EMCR21;TPCC_TPCC_EMCR_EMCR22;TPCC_TPCC_EMCR_EMCR23; TPCC_TPCC_EMCR_EMCR24;TPCC_TPCC_EMCR_EMCR25;TPCC_TPCC_EMCR_EMCR26; TPCC_TPCC_EMCR_EMCR27;TPCC_TPCC_EMCR_EMCR28;TPCC_TPCC_EMCR_EMCR29; TPCC_TPCC_EMCR_EMCR30;TPCC_TPCC_EMCR_EMCR31;
TPCC_TPCC_EMCRH_EMCR32;TPCC_TPCC_EMCRH_EMCR33;TPCC_TPCC_EMCRH_EMCR34 TPCC_TPCC_EMCRH_EMCR35;TPCC_TPCC_EMCRH_EMCR36;TPCC_TPCC_EMCRH_EMCR37 TPCC_TPCC_EMCRH_EMCR38;TPCC_TPCC_EMCRH_EMCR39;TPCC_TPCC_EMCRH_EMCR40 TPCC_TPCC_EMCRH_EMCR41;TPCC_TPCC_EMCRH_EMCR42;TPCC_TPCC_EMCRH_EMCR43 TPCC_TPCC_EMCRH_EMCR44;TPCC_TPCC_EMCRH_EMCR45;TPCC_TPCC_EMCRH_EMCR46 TPCC_TPCC_EMCRH_EMCR47;TPCC_TPCC_EMCRH_EMCR48;TPCC_TPCC_EMCRH_EMCR49 TPCC_TPCC_EMCRH_EMCR50;TPCC_TPCC_EMCRH_EMCR51;TPCC_TPCC_EMCRH_EMCR52 TPCC_TPCC_EMCRH_EMCR53;TPCC_TPCC_EMCRH_EMCR54;TPCC_TPCC_EMCRH_EMCR55 TPCC_TPCC_EMCRH_EMCR56;TPCC_TPCC_EMCRH_EMCR57;TPCC_TPCC_EMCRH_EMCR58 TPCC_TPCC_EMCRH_EMCR59;TPCC_TPCC_EMCRH_EMCR60;TPCC_TPCC_EMCRH_EMCR61 TPCC_TPCC_EMCRH_EMCR62;TPCC_TPCC_EMCRH_EMCR63,
TPCC_TPCC_SECR_SECR0=1;TPCC_TPCC_SECR_SECR1=1;TPCC_TPCC_SECR_SECR2=1; TPCC_TPCC_SECR_SECR3=1;TPCC_TPCC_SECR_SECR4=1;TPCC_TPCC_SECR_SECR5=1; TPCC_TPCC_SECR_SECR6=1;TPCC_TPCC_SECR_SECR7=1;TPCC_TPCC_SECR_SECR8=1; TPCC_TPCC_SECR_SECR9=1;TPCC_TPCC_SECR_SECR10=1;TPCC_TPCC_SECR_SECR11=1; TPCC_TPCC_SECR_SECR12=1;TPCC_TPCC_SECR_SECR13=1;TPCC_TPCC_SECR_SECR14=1; TPCC_TPCC_SECR_SECR15=1;TPCC_TPCC_SECR_SECR16=1;TPCC_TPCC_SECR_SECR17=1; TPCC_TPCC_SECR_SECR18=1;TPCC_TPCC_SECR_SECR19=1;TPCC_TPCC_SECR_SECR20=1; TPCC_TPCC_SECR_SECR21=1;TPCC_TPCC_SECR_SECR22=1;TPCC_TPCC_SECR_SECR23=1; TPCC_TPCC_SECR_SECR24=1;TPCC_TPCC_SECR_SECR25=1;TPCC_TPCC_SECR_SECR26=1; TPCC_TPCC_SECR_SECR27=1;TPCC_TPCC_SECR_SECR28=1;TPCC_TPCC_SECR_SECR29=1; TPCC_TPCC_SECR_SECR30=1;TPCC_TPCC_SECR_SECR31=1;
TPCC_TPCC_SECRH_SECR32=1;TPCC_TPCC_SECRH_SECR33=1;TPCC_TPCC_SECRH_SECR34=1; TPCC_TPCC_SECRH_SECR35=1;TPCC_TPCC_SECRH_SECR36=1;TPCC_TPCC_SECRH_SECR37=1; TPCC_TPCC_SECRH_SECR38=1;TPCC_TPCC_SECRH_SECR39=1;TPCC_TPCC_SECRH_SECR40=1; TPCC_TPCC_SECRH_SECR41=1;TPCC_TPCC_SECRH_SECR42=1;TPCC_TPCC_SECRH_SECR43=1; TPCC_TPCC_SECRH_SECR44=1;TPCC_TPCC_SECRH_SECR45=1;TPCC_TPCC_SECRH_SECR46=1; TPCC_TPCC_SECRH_SECR47=1;TPCC_TPCC_SECRH_SECR48=1;TPCC_TPCC_SECRH_SECR49=1; TPCC_TPCC_SECRH_SECR50=1;TPCC_TPCC_SECRH_SECR51=1;TPCC_TPCC_SECRH_SECR52=1; TPCC_TPCC_SECRH_SECR53=1;TPCC_TPCC_SECRH_SECR54=1;TPCC_TPCC_SECRH_SECR55=1; TPCC_TPCC_SECRH_SECR56=1;TPCC_TPCC_SECRH_SECR57=1;TPCC_TPCC_SECRH_SECR58=1; TPCC_TPCC_SECRH_SECR59=1;TPCC_TPCC_SECRH_SECR60=1;TPCC_TPCC_SECRH_SECR61=1; TPCC_TPCC_SECRH_SECR62=1;TPCC_TPCC_SECRH_SECR63=1;
TPCC_TPCC_QEMCR_QEMCR0;TPCC_TPCC_QEMCR_QEMCR1;TPCC_TPCC_QEMCR_QEMCR2; TPCC_TPCC_QEMCR_QEMCR3;TPCC_TPCC_QEMCR_QEMCR4;TPCC_TPCC_QEMCR_QEMCR5; TPCC_TPCC_QEMCR_QEMCR6;TPCC_TPCC_QEMCR_QEMCR7,
TPCC_TPCC_QSECR_QSECR0=1;TPCC_TPCC_QSECR_QSECR1=1;TPCC_TPCC_QSECR_QSECR2=1; TPCC_TPCC_QSECR_QSECR3=1;TPCC_TPCC_QSECR_QSECR4=1;TPCC_TPCC_QSECR_QSECR5=1; TPCC_TPCC_QSECR_QSECR6=1;TPCC_TPCC_QSECR_QSECR7=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 0; hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status); ... // Enable Channel CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL); ...
=============================================================================
CSL_Status CSL_edma3HwChannelSetupParam | ( | CSL_Edma3ChannelHandle | hEdma, | |
Uint16 | paramNum | |||
) |
============================================================================
CSL_edma3HwChannelSetupParam
Description
The function maps a DMA/QDMA channel to the specific PARAM Entry.
Arguments
hEdma Channel Handle paramNum Parameter Entry
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Pre Condition
CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before this API can be invoked
Post Condition
Channel is mapped to the PARAM Entry.
Writes
TPCC_TPCC_DCHMAP_PAENTRY;
TPCC_TPCC_QCHMAP_PAENTRY
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3ChannelAttr chAttr; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Channel 0 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 0; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ... // Map the channel to PARAM Entry 1 CSL_edma3HwChannelSetupParam(hChannel, 1); ...
=============================================================================
CSL_Status CSL_edma3HwChannelSetupQue | ( | CSL_Edma3ChannelHandle | hEdma, | |
CSL_Edma3Que | evtQue | |||
) |
============================================================================
CSL_edma3HwChannelSetupQue
Description
The function maps the DMA/QDMA channels to the specified event queue.
Arguments
hEdma Channel Handle evtQue Queue Setup
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Pre Condition
CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before this API can be invoked
Post Condition
Sets up the channel to Queue mapping
Writes
TPCC_TPCC_QDMAQNUM_E0;TPCC_TPCC_QDMAQNUM_E1;TPCC_TPCC_QDMAQNUM_E2; TPCC_TPCC_QDMAQNUM_E3;TPCC_TPCC_QDMAQNUM_E4;TPCC_TPCC_QDMAQNUM_E5; TPCC_TPCC_QDMAQNUM_E6;TPCC_TPCC_QDMAQNUM_E7;
TPCC_TPCC_DMAQNUM_E0;TPCC_TPCC_DMAQNUM_E1;TPCC_TPCC_DMAQNUM_E2; TPCC_TPCC_DMAQNUM_E3;TPCC_TPCC_DMAQNUM_E4;TPCC_TPCC_DMAQNUM_E5; TPCC_TPCC_DMAQNUM_E6;TPCC_TPCC_DMAQNUM_E7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3ChannelAttr chAttr; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Channel 1 Open in context of Shadow region 0 chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 16; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ... // Map the channel 1 to Event Queue 3. CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_3); ...
=============================================================================
CSL_Status CSL_edma3HwChannelSetupTriggerWord | ( | CSL_Edma3ChannelHandle | hEdma, | |
Uint8 | triggerWord | |||
) |
============================================================================
CSL_edma3HwChannelSetupTriggerWord
Description
The function is used to setup the trigger word for QDMA Channels.
Arguments
hEdma Channel Handle triggerWord Trigger Word to be configured.
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Pre Condition
CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before this API can be invoked
Post Condition
Sets up the QDMA Channel to trigger Word
Writes
TPCC_TPCC_QCHMAP_TRWORD
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3ChannelAttr chAttr; CSL_Edma3ChannelObj chObj; CSL_Edma3ChannelHandle hChannel; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Channel 16 Open in context of Shadow region 0 (This is a QDMA Channel) chAttr.regionNum = CSL_EDMA3_REGION_0; chAttr.chaNum = 16; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); ... // Sets up the QDMA Channel 0 trigger Word to the 3rd trigger word. CSL_edma3HwChannelSetupTriggerWord(hChannel,3); ...
=============================================================================
CSL_Status CSL_edma3HwControl | ( | CSL_Edma3Handle | hMod, | |
CSL_Edma3HwControlCmd | cmd, | |||
void * | cmdArg | |||
) |
============================================================================
CSL_edma3HwControl
Description
This API takes a command with an optional argument and performs the appropriate action. This can be used to perform various operations on the EDMA module.
Arguments
hMod EDMA Module Handle cmd Command which needs to be executed. cmdArg Pointer to the argument specific to the command
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVCMD (The command passed is invalid)
Pre Condition
Functions CSL_edma3Init(), CSL_edma3Open() must be called successfully in that order before this API can be invoked
Post Condition
EDMA registers are configured according to the command and the command arguments. The command determines which registers are modified.
Writes
TPCC_TPCC_MPPAG;TPCC_TPCC_MPPA;
TPCC_TPCC_MPFCR_MPFCLR=1;
TPCC_TPCC_DRA_DRAE_E0=1;TPCC_TPCC_DRA_DRAE_E1=1;TPCC_TPCC_DRA_DRAE_E2=1; TPCC_TPCC_DRA_DRAE_E3=1;TPCC_TPCC_DRA_DRAE_E4=1;TPCC_TPCC_DRA_DRAE_E5=1; TPCC_TPCC_DRA_DRAE_E6=1;TPCC_TPCC_DRA_DRAE_E7=1;TPCC_TPCC_DRA_DRAE_E8=1; TPCC_TPCC_DRA_DRAE_E9=1;TPCC_TPCC_DRA_DRAE_E10=1;TPCC_TPCC_DRA_DRAE_E11=1; TPCC_TPCC_DRA_DRAE_E12=1;TPCC_TPCC_DRA_DRAE_E13=1;TPCC_TPCC_DRA_DRAE_E14=1; TPCC_TPCC_DRA_DRAE_E15=1;TPCC_TPCC_DRA_DRAE_E16=1;TPCC_TPCC_DRA_DRAE_E17=1; TPCC_TPCC_DRA_DRAE_E18=1;TPCC_TPCC_DRA_DRAE_E19=1;TPCC_TPCC_DRA_DRAE_E20=1; TPCC_TPCC_DRA_DRAE_E21=1;TPCC_TPCC_DRA_DRAE_E22=1;TPCC_TPCC_DRA_DRAE_E23=1; TPCC_TPCC_DRA_DRAE_E24=1;TPCC_TPCC_DRA_DRAE_E25=1;TPCC_TPCC_DRA_DRAE_E26=1; TPCC_TPCC_DRA_DRAE_E27=1;TPCC_TPCC_DRA_DRAE_E28=1;TPCC_TPCC_DRA_DRAE_E29=1; TPCC_TPCC_DRA_DRAE_E30=1;TPCC_TPCC_DRA_DRAE_E31=1;
TPCC_TPCC_DRA_DRAEH_E32=1;TPCC_TPCC_DRA_DRAEH_E33=1;TPCC_TPCC_DRA_DRAEH_E34=1; TPCC_TPCC_DRA_DRAEH_E35=1;TPCC_TPCC_DRA_DRAEH_E36=1;TPCC_TPCC_DRA_DRAEH_E37=1; TPCC_TPCC_DRA_DRAEH_E38=1;TPCC_TPCC_DRA_DRAEH_E39=1;TPCC_TPCC_DRA_DRAEH_E40=1; TPCC_TPCC_DRA_DRAEH_E41=1;TPCC_TPCC_DRA_DRAEH_E42=1;TPCC_TPCC_DRA_DRAEH_E43=1; TPCC_TPCC_DRA_DRAEH_E44=1;TPCC_TPCC_DRA_DRAEH_E45=1;TPCC_TPCC_DRA_DRAEH_E46=1; TPCC_TPCC_DRA_DRAEH_E47=1;TPCC_TPCC_DRA_DRAEH_E48=1;TPCC_TPCC_DRA_DRAEH_E49=1; TPCC_TPCC_DRA_DRAEH_E50=1;TPCC_TPCC_DRA_DRAEH_E51=1;TPCC_TPCC_DRA_DRAEH_E52=1; TPCC_TPCC_DRA_DRAEH_E53=1;TPCC_TPCC_DRA_DRAEH_E54=1;TPCC_TPCC_DRA_DRAEH_E55=1; TPCC_TPCC_DRA_DRAEH_E56=1;TPCC_TPCC_DRA_DRAEH_E57=1;TPCC_TPCC_DRA_DRAEH_E58=1; TPCC_TPCC_DRA_DRAEH_E59=1;TPCC_TPCC_DRA_DRAEH_E60=1;TPCC_TPCC_DRA_DRAEH_E61=1; TPCC_TPCC_DRA_DRAEH_E62=1;TPCC_TPCC_DRA_DRAEH_E63=1;
TPCC_TPCC_DRA_DRAE_E0=0;TPCC_TPCC_DRA_DRAE_E1=0;TPCC_TPCC_DRA_DRAE_E2=0; TPCC_TPCC_DRA_DRAE_E3=0;TPCC_TPCC_DRA_DRAE_E4=0;TPCC_TPCC_DRA_DRAE_E5=0; TPCC_TPCC_DRA_DRAE_E6=0;TPCC_TPCC_DRA_DRAE_E7=0;TPCC_TPCC_DRA_DRAE_E8=0; TPCC_TPCC_DRA_DRAE_E9=0;TPCC_TPCC_DRA_DRAE_E10=0;TPCC_TPCC_DRA_DRAE_E11=0; TPCC_TPCC_DRA_DRAE_E12=0;TPCC_TPCC_DRA_DRAE_E13=0;TPCC_TPCC_DRA_DRAE_E14=0; TPCC_TPCC_DRA_DRAE_E15=0;TPCC_TPCC_DRA_DRAE_E16=0;TPCC_TPCC_DRA_DRAE_E17=0; TPCC_TPCC_DRA_DRAE_E18=0;TPCC_TPCC_DRA_DRAE_E19=0;TPCC_TPCC_DRA_DRAE_E20=0; TPCC_TPCC_DRA_DRAE_E21=0;TPCC_TPCC_DRA_DRAE_E22=0;TPCC_TPCC_DRA_DRAE_E23=0; TPCC_TPCC_DRA_DRAE_E24=0;TPCC_TPCC_DRA_DRAE_E25=0;TPCC_TPCC_DRA_DRAE_E26=0; TPCC_TPCC_DRA_DRAE_E27=0;TPCC_TPCC_DRA_DRAE_E28=0;TPCC_TPCC_DRA_DRAE_E29=0; TPCC_TPCC_DRA_DRAE_E30=0;TPCC_TPCC_DRA_DRAE_E31=0;
TPCC_TPCC_DRA_DRAEH_E32=0;TPCC_TPCC_DRA_DRAEH_E33=0;TPCC_TPCC_DRA_DRAEH_E34=0; TPCC_TPCC_DRA_DRAEH_E35=0;TPCC_TPCC_DRA_DRAEH_E36=0;TPCC_TPCC_DRA_DRAEH_E37=0; TPCC_TPCC_DRA_DRAEH_E38=0;TPCC_TPCC_DRA_DRAEH_E39=0;TPCC_TPCC_DRA_DRAEH_E40=0; TPCC_TPCC_DRA_DRAEH_E41=0;TPCC_TPCC_DRA_DRAEH_E42=0;TPCC_TPCC_DRA_DRAEH_E43=0; TPCC_TPCC_DRA_DRAEH_E44=0;TPCC_TPCC_DRA_DRAEH_E45=0;TPCC_TPCC_DRA_DRAEH_E46=0; TPCC_TPCC_DRA_DRAEH_E47=0;TPCC_TPCC_DRA_DRAEH_E48=0;TPCC_TPCC_DRA_DRAEH_E49=0; TPCC_TPCC_DRA_DRAEH_E50=0;TPCC_TPCC_DRA_DRAEH_E51=0;TPCC_TPCC_DRA_DRAEH_E52=0; TPCC_TPCC_DRA_DRAEH_E53=0;TPCC_TPCC_DRA_DRAEH_E54=0;TPCC_TPCC_DRA_DRAEH_E55=0; TPCC_TPCC_DRA_DRAEH_E56=0;TPCC_TPCC_DRA_DRAEH_E57=0;TPCC_TPCC_DRA_DRAEH_E58=0; TPCC_TPCC_DRA_DRAEH_E59=0;TPCC_TPCC_DRA_DRAEH_E60=0;TPCC_TPCC_DRA_DRAEH_E61=0; TPCC_TPCC_DRA_DRAEH_E62=0;TPCC_TPCC_DRA_DRAEH_E63=0;
TPCC_TPCC_QRAE_E0=1;TPCC_TPCC_QRAE_E1=1;TPCC_TPCC_QRAE_E2=1; TPCC_TPCC_QRAE_E3=1;TPCC_TPCC_QRAE_E4=1;TPCC_TPCC_QRAE_E5=1; TPCC_TPCC_QRAE_E6=1;TPCC_TPCC_QRAE_E7=1;
TPCC_TPCC_QRAE_E0=0;TPCC_TPCC_QRAE_E1=0;TPCC_TPCC_QRAE_E2=0; TPCC_TPCC_QRAE_E3=0;TPCC_TPCC_QRAE_E4=0;TPCC_TPCC_QRAE_E5=0; TPCC_TPCC_QRAE_E6=0;TPCC_TPCC_QRAE_E7=0;
TPCC_TPCC_QUEPRI_PRIQ0;TPCC_TPCC_QUEPRI_PRIQ1;TPCC_TPCC_QUEPRI_PRIQ2; TPCC_TPCC_QUEPRI_PRIQ3;TPCC_TPCC_QUEPRI_PRIQ4;TPCC_TPCC_QUEPRI_PRIQ5; TPCC_TPCC_QUEPRI_PRIQ6;TPCC_TPCC_QUEPRI_PRIQ7;
TPCC_TPCC_QWMTHRA_Q0;TPCC_TPCC_QWMTHRA_Q1;TPCC_TPCC_QWMTHRA_Q2; TPCC_TPCC_QWMTHRA_Q3;
TPCC_TPCC_QWMTHRB_Q4;TPCC_TPCC_QWMTHRB_Q1;TPCC_TPCC_QWMTHRB_Q2; TPCC_TPCC_QWMTHRB_Q3;
TPCC_TPCC_EEVAL_EVAL=1;
TPCC_TPCC_ICR,TPCC_TPCC_ICRH;
TPCC_TPCC_IESR_IESR0=1;TPCC_TPCC_IESR_IESR1=1;TPCC_TPCC_IESR_IESR2=1; TPCC_TPCC_IESR_IESR3=1;TPCC_TPCC_IESR_IESR4=1;TPCC_TPCC_IESR_IESR5=1; TPCC_TPCC_IESR_IESR6=1;TPCC_TPCC_IESR_IESR7=1;TPCC_TPCC_IESR_IESR8=1; TPCC_TPCC_IESR_IESR9=1;TPCC_TPCC_IESR_IESR10=1;TPCC_TPCC_IESR_IESR11=1; TPCC_TPCC_IESR_IESR12=1;TPCC_TPCC_IESR_IESR13=1;TPCC_TPCC_IESR_IESR14=1; TPCC_TPCC_IESR_IESR15=1;TPCC_TPCC_IESR_IESR16=1;TPCC_TPCC_IESR_IESR17=1; TPCC_TPCC_IESR_IESR18=1;TPCC_TPCC_IESR_IESR19=1;TPCC_TPCC_IESR_IESR20=1; TPCC_TPCC_IESR_IESR21=1;TPCC_TPCC_IESR_IESR22=1;TPCC_TPCC_IESR_IESR23=1; TPCC_TPCC_IESR_IESR24=1;TPCC_TPCC_IESR_IESR25=1;TPCC_TPCC_IESR_IESR26=1; TPCC_TPCC_IESR_IESR27=1;TPCC_TPCC_IESR_IESR28=1;TPCC_TPCC_IESR_IESR29=1; TPCC_TPCC_IESR_IESR30=1;TPCC_TPCC_IESR_IESR31=1;
TPCC_TPCC_IESRH_IESR32=1;TPCC_TPCC_IESRH_IESR33=1;TPCC_TPCC_IESRH_IESR34=1; TPCC_TPCC_IESRH_IESR35=1;TPCC_TPCC_IESRH_IESR36=1;TPCC_TPCC_IESRH_IESR37=1; TPCC_TPCC_IESRH_IESR38=1;TPCC_TPCC_IESRH_IESR39=1;TPCC_TPCC_IESRH_IESR40=1; TPCC_TPCC_IESRH_IESR41=1;TPCC_TPCC_IESRH_IESR42=1;TPCC_TPCC_IESRH_IESR43=1; TPCC_TPCC_IESRH_IESR44=1;TPCC_TPCC_IESRH_IESR45=1;TPCC_TPCC_IESRH_IESR46=1; TPCC_TPCC_IESRH_IESR47=1;TPCC_TPCC_IESRH_IESR48=1;TPCC_TPCC_IESRH_IESR49=1; TPCC_TPCC_IESRH_IESR50=1;TPCC_TPCC_IESRH_IESR51=1;TPCC_TPCC_IESRH_IESR52=1; TPCC_TPCC_IESRH_IESR53=1;TPCC_TPCC_IESRH_IESR54=1;TPCC_TPCC_IESRH_IESR55=1; TPCC_TPCC_IESRH_IESR56=1;TPCC_TPCC_IESRH_IESR57=1;TPCC_TPCC_IESRH_IESR58=1; TPCC_TPCC_IESRH_IESR59=1;TPCC_TPCC_IESRH_IESR60=1;TPCC_TPCC_IESRH_IESR61=1; TPCC_TPCC_IESRH_IESR62=1;TPCC_TPCC_IESRH_IESR63=1;
TPCC_TPCC_IECR_IECR0=1;TPCC_TPCC_IECR_IECR1=1;TPCC_TPCC_IECR_IECR2=1; TPCC_TPCC_IECR_IECR3=1;TPCC_TPCC_IECR_IECR4=1;TPCC_TPCC_IECR_IECR5=1; TPCC_TPCC_IECR_IECR6=1;TPCC_TPCC_IECR_IECR7=1;TPCC_TPCC_IECR_IECR8=1; TPCC_TPCC_IECR_IECR9=1;TPCC_TPCC_IECR_IECR10=1;TPCC_TPCC_IECR_IECR11=1; TPCC_TPCC_IECR_IECR12=1;TPCC_TPCC_IECR_IECR13=1;TPCC_TPCC_IECR_IECR14=1; TPCC_TPCC_IECR_IECR15=1;TPCC_TPCC_IECR_IECR16=1;TPCC_TPCC_IECR_IECR17=1; TPCC_TPCC_IECR_IECR18=1;TPCC_TPCC_IECR_IECR19=1;TPCC_TPCC_IECR_IECR20=1; TPCC_TPCC_IECR_IECR21=1;TPCC_TPCC_IECR_IECR22=1;TPCC_TPCC_IECR_IECR23=1; TPCC_TPCC_IECR_IECR24=1;TPCC_TPCC_IECR_IECR25=1;TPCC_TPCC_IECR_IECR26=1; TPCC_TPCC_IECR_IECR27=1;TPCC_TPCC_IECR_IECR28=1;TPCC_TPCC_IECR_IECR29=1; TPCC_TPCC_IECR_IECR30=1;TPCC_TPCC_IECR_IECR31=1;
TPCC_TPCC_IECRH_IECR32=1;TPCC_TPCC_IECRH_IECR33=1;TPCC_TPCC_IECRH_IECR34=1; TPCC_TPCC_IECRH_IECR35=1;TPCC_TPCC_IECRH_IECR36=1;TPCC_TPCC_IECRH_IECR37=1; TPCC_TPCC_IECRH_IECR38=1;TPCC_TPCC_IECRH_IECR39=1;TPCC_TPCC_IECRH_IECR40=1; TPCC_TPCC_IECRH_IECR41=1;TPCC_TPCC_IECRH_IECR42=1;TPCC_TPCC_IECRH_IECR43=1; TPCC_TPCC_IECRH_IECR44=1;TPCC_TPCC_IECRH_IECR45=1;TPCC_TPCC_IECRH_IECR46=1; TPCC_TPCC_IECRH_IECR47=1;TPCC_TPCC_IECRH_IECR48=1;TPCC_TPCC_IECRH_IECR49=1; TPCC_TPCC_IECRH_IECR50=1;TPCC_TPCC_IECRH_IECR51=1;TPCC_TPCC_IECRH_IECR52=1; TPCC_TPCC_IECRH_IECR53=1;TPCC_TPCC_IECRH_IECR54=1;TPCC_TPCC_IECRH_IECR55=1; TPCC_TPCC_IECRH_IECR56=1;TPCC_TPCC_IECRH_IECR57=1;TPCC_TPCC_IECRH_IECR58=1; TPCC_TPCC_IECRH_IECR59=1;TPCC_TPCC_IECRH_IECR60=1;TPCC_TPCC_IECRH_IECR61=1; TPCC_TPCC_IECRH_IECR62=1;TPCC_TPCC_IECRH_IECR63=1;
TPCC_TPCC_IEVAL_EVAL=1;
TPCC_TPCC_CCERRCLR_QTHRXD0;TPCC_TPCC_CCERRCLR_QTHRXD1;TPCC_TPCC_CCERRCLR_QTHRXD2; TPCC_TPCC_CCERRCLR_QTHRXD3;TPCC_TPCC_CCERRCLR_QTHRXD4;TPCC_TPCC_CCERRCLR_QTHRXD5; TPCC_TPCC_CCERRCLR_QTHRXD6;TPCC_TPCC_CCERRCLR_QTHRXD7, TPCC_TPCC_CCERR_TCCERR;
TPCC_TPCC_EMCR,TPCC_TPCC_EMCRH,TPCC_TPCC_QEMCR
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3CmdDrae regionAccess; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // DRAE Enable(Bits 0-15) for the Shadow Region 0. regionAccess.region = CSL_EDMA3_REGION_0 ; regionAccess.drae = 0xFFFF ; regionAccess.draeh = 0x0000 ; CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, ®ionAccess); ...
=============================================================================
CSL_Status CSL_edma3HwSetup | ( | CSL_Edma3Handle | hMod, | |
CSL_Edma3HwSetup * | setup | |||
) |
============================================================================
CSL_edma3HwSetup
Description
This function does the setup for all DMA/QDMA channels by doing the following operations:-
Arguments
hMod Edma module Handle setup Pointer to the setup structure
Return Value CSL_Status
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Pre Condition
CSL_edma3Init(), CSL_edma3Open() must be called successfully in that order before this API can be invoked
Post Condition
EDMA registers are configured according to the hardware setup parameters
Writes
TPCC_TPCC_DCHMAP_PAENTRY,
TPCC_TPCC_DMAQNUM_E0;TPCC_TPCC_DMAQNUM_E1;TPCC_TPCC_DMAQNUM_E2; TPCC_TPCC_DMAQNUM_E3;TPCC_TPCC_DMAQNUM_E4;TPCC_TPCC_DMAQNUM_E5; TPCC_TPCC_DMAQNUM_E6;TPCC_TPCC_DMAQNUM_E7;
TPCC_TPCC_QCHMAP_PAENTRY,
TPCC_TPCC_QCHMAP_TRWORD,
TPCC_TPCC_QDMAQNUM_E0;TPCC_TPCC_QDMAQNUM_E1;TPCC_TPCC_QDMAQNUM_E2; TPCC_TPCC_QDMAQNUM_E3;TPCC_TPCC_QDMAQNUM_E4;TPCC_TPCC_QDMAQNUM_E5; TPCC_TPCC_QDMAQNUM_E6;TPCC_TPCC_QDMAQNUM_E7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3HwSetup hwSetup; CSL_Edma3HwDmaChannelSetup dmahwSetup[64]; CSL_Edma3HwQdmaChannelSetup qdmahwSetup[8]; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Module Setup hwSetup.dmaChaSetup = &dmahwSetup[0]; hwSetup.qdmaChaSetup = &qdmaSetup[0]; CSL_edma3HwSetup(hModule,&hwSetup); ...
=============================================================================
CSL_Status CSL_edma3Init | ( | CSL_Edma3Context * | pContext | ) |
============================================================================
CSL_edma3Init
Description
This is the initialization function for the EDMA CSL. The function must be called before calling any other API from this CSL.This function is idem-potent. Currently, the function just return status CSL_SOK, without doing anything.
Arguments
pContext Pointer to module-context. As EDMA doesn't have any context based information user is expected to pass NULL.
Return Value
Always returns CSL_SOK
Pre Condition
None
Post Condition
The CSL for EDMA is initialized
Affects
None
Example
// Initialize the EDMA3 Module. CSL_edma3Init(NULL); ... // All EDMA Functions should follow this. ...
=============================================================================
CSL_IDEF_INLINE void CSL_edma3InterruptEval | ( | CSL_Edma3Handle | hModule, | |
Int | region | |||
) |
============================================================================
CSL_edma3InterruptEval
Description
The API is used to set the EVAL bit which will cause an interrupt to be generated if any enabled interrupts are still pending.
Arguments
hModule Module Handle region Region (Shadown Region or Global)
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_IEVAL_EVAL=1
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; CSL_BitMask32 edmaIntrLo; CSL_BitMask32 edmaIntrHi; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Interrupt Evaluate for Global Region. status = CSL_edma3InterruptEval(hModule, CSL_EDMA3_REGION_GLOBAL); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3InterruptHiDisable | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 | intrHi | |||
) |
============================================================================
CSL_edma3InterruptHiDisable
Description
The API disables the specified high interrupt Number.
Arguments
hModule Module Handle region Region (Shadow or Global) intrHi Interrupt 32-63 (BitMask32) to be disabled
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_IECRH_IECR32=1;TPCC_TPCC_IECRH_IECR33=1;TPCC_TPCC_IECRH_IECR34=1; TPCC_TPCC_IECRH_IECR35=1;TPCC_TPCC_IECRH_IECR36=1;TPCC_TPCC_IECRH_IECR37=1; TPCC_TPCC_IECRH_IECR38=1;TPCC_TPCC_IECRH_IECR39=1;TPCC_TPCC_IECRH_IECR40=1; TPCC_TPCC_IECRH_IECR41=1;TPCC_TPCC_IECRH_IECR42=1;TPCC_TPCC_IECRH_IECR43=1; TPCC_TPCC_IECRH_IECR44=1;TPCC_TPCC_IECRH_IECR45=1;TPCC_TPCC_IECRH_IECR46=1; TPCC_TPCC_IECRH_IECR47=1;TPCC_TPCC_IECRH_IECR48=1;TPCC_TPCC_IECRH_IECR49=1; TPCC_TPCC_IECRH_IECR50=1;TPCC_TPCC_IECRH_IECR51=1;TPCC_TPCC_IECRH_IECR52=1; TPCC_TPCC_IECRH_IECR53=1;TPCC_TPCC_IECRH_IECR54=1;TPCC_TPCC_IECRH_IECR55=1; TPCC_TPCC_IECRH_IECR56=1;TPCC_TPCC_IECRH_IECR57=1;TPCC_TPCC_IECRH_IECR58=1; TPCC_TPCC_IECRH_IECR59=1;TPCC_TPCC_IECRH_IECR60=1;TPCC_TPCC_IECRH_IECR61=1; TPCC_TPCC_IECRH_IECR62=1;TPCC_TPCC_IECRH_IECR63=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Interrupts 32 disabled for Global Region. CSL_edma3InterruptHiDisable(hModule, CSL_EDMA3_REGION_GLOBAL, 0x1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3InterruptHiEnable | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 | intrHi | |||
) |
============================================================================
CSL_edma3InterruptHiEnable
Description
The API enables the specific High interrupt.
Arguments
hModule Module Handle region Region (Shadow or Global) intrHi Interrupt 32-63 (BitMask32) to be enabled
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_IESRH_IESR32=1;TPCC_TPCC_IESRH_IESR33=1;TPCC_TPCC_IESRH_IESR34=1; TPCC_TPCC_IESRH_IESR35=1;TPCC_TPCC_IESRH_IESR36=1;TPCC_TPCC_IESRH_IESR37=1; TPCC_TPCC_IESRH_IESR38=1;TPCC_TPCC_IESRH_IESR39=1;TPCC_TPCC_IESRH_IESR40=1; TPCC_TPCC_IESRH_IESR41=1;TPCC_TPCC_IESRH_IESR42=1;TPCC_TPCC_IESRH_IESR43=1; TPCC_TPCC_IESRH_IESR44=1;TPCC_TPCC_IESRH_IESR45=1;TPCC_TPCC_IESRH_IESR46=1; TPCC_TPCC_IESRH_IESR47=1;TPCC_TPCC_IESRH_IESR48=1;TPCC_TPCC_IESRH_IESR49=1; TPCC_TPCC_IESRH_IESR50=1;TPCC_TPCC_IESRH_IESR51=1;TPCC_TPCC_IESRH_IESR52=1; TPCC_TPCC_IESRH_IESR53=1;TPCC_TPCC_IESRH_IESR54=1;TPCC_TPCC_IESRH_IESR55=1; TPCC_TPCC_IESRH_IESR56=1;TPCC_TPCC_IESRH_IESR57=1;TPCC_TPCC_IESRH_IESR58=1; TPCC_TPCC_IESRH_IESR59=1;TPCC_TPCC_IESRH_IESR60=1;TPCC_TPCC_IESRH_IESR61=1; TPCC_TPCC_IESRH_IESR62=1;TPCC_TPCC_IESRH_IESR63=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Interrupts 32 enabled for the global region. CSL_edma3InterruptHiEnable(hModule,CSL_EDMA3_REGION_GLOBAL, 0x1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3InterruptLoDisable | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 | intrLo | |||
) |
============================================================================
CSL_edma3InterruptLoDisable
Description
The API disables the specified low interrupt Number.
Arguments
hModule Module Handle region Region (Shadow or Global) intrLo Interrupt 0-31 (BitMask32) to be disabled
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_IECR_IECR0=1;TPCC_TPCC_IECR_IECR1=1;TPCC_TPCC_IECR_IECR2=1; TPCC_TPCC_IECR_IECR3=1;TPCC_TPCC_IECR_IECR4=1;TPCC_TPCC_IECR_IECR5=1; TPCC_TPCC_IECR_IECR6=1;TPCC_TPCC_IECR_IECR7=1;TPCC_TPCC_IECR_IECR8=1; TPCC_TPCC_IECR_IECR9=1;TPCC_TPCC_IECR_IECR10=1;TPCC_TPCC_IECR_IECR11=1; TPCC_TPCC_IECR_IECR12=1;TPCC_TPCC_IECR_IECR13=1;TPCC_TPCC_IECR_IECR14=1; TPCC_TPCC_IECR_IECR15=1;TPCC_TPCC_IECR_IECR16=1;TPCC_TPCC_IECR_IECR17=1; TPCC_TPCC_IECR_IECR18=1;TPCC_TPCC_IECR_IECR19=1;TPCC_TPCC_IECR_IECR20=1; TPCC_TPCC_IECR_IECR21=1;TPCC_TPCC_IECR_IECR22=1;TPCC_TPCC_IECR_IECR23=1; TPCC_TPCC_IECR_IECR24=1;TPCC_TPCC_IECR_IECR25=1;TPCC_TPCC_IECR_IECR26=1; TPCC_TPCC_IECR_IECR27=1;TPCC_TPCC_IECR_IECR28=1;TPCC_TPCC_IECR_IECR29=1; TPCC_TPCC_IECR_IECR30=1;TPCC_TPCC_IECR_IECR31=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Interrupts 5-7 disabled for Global Region. CSL_edma3InterruptLoDisable(hModule, CSL_EDMA3_REGION_GLOBAL, 0x000000E0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3InterruptLoEnable | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 | intrLo | |||
) |
============================================================================
CSL_edma3InterruptLoEnable
Description
The API enables the specific lower interrupts
Arguments
hModule Module Handle region Region (Shadow or Global) intrLo Interrupt 0-31 (BitMask32) to be enabled
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_IESR_IESR0=1;TPCC_TPCC_IESR_IESR1=1;TPCC_TPCC_IESR_IESR2=1; TPCC_TPCC_IESR_IESR3=1;TPCC_TPCC_IESR_IESR4=1;TPCC_TPCC_IESR_IESR5=1; TPCC_TPCC_IESR_IESR6=1;TPCC_TPCC_IESR_IESR7=1;TPCC_TPCC_IESR_IESR8=1; TPCC_TPCC_IESR_IESR9=1;TPCC_TPCC_IESR_IESR10=1;TPCC_TPCC_IESR_IESR11=1; TPCC_TPCC_IESR_IESR12=1;TPCC_TPCC_IESR_IESR13=1;TPCC_TPCC_IESR_IESR14=1; TPCC_TPCC_IESR_IESR15=1;TPCC_TPCC_IESR_IESR16=1;TPCC_TPCC_IESR_IESR17=1; TPCC_TPCC_IESR_IESR18=1;TPCC_TPCC_IESR_IESR19=1;TPCC_TPCC_IESR_IESR20=1; TPCC_TPCC_IESR_IESR21=1;TPCC_TPCC_IESR_IESR22=1;TPCC_TPCC_IESR_IESR23=1; TPCC_TPCC_IESR_IESR24=1;TPCC_TPCC_IESR_IESR25=1;TPCC_TPCC_IESR_IESR26=1; TPCC_TPCC_IESR_IESR27=1;TPCC_TPCC_IESR_IESR28=1;TPCC_TPCC_IESR_IESR29=1; TPCC_TPCC_IESR_IESR30=1;TPCC_TPCC_IESR_IESR31=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Interrupts 5-7 enabled for the global region. CSL_edma3InterruptLoEnable(hModule,CSL_EDMA3_REGION_GLOBAL, 0x000000E0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3IsDMAChannelEventPending | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel, | |||
Bool * | response | |||
) |
============================================================================
CSL_edma3IsDMAChannelEventPending
Description
The function gets the status of the specified DMA channel i.e. if there is a pending event on the specific channel.
Arguments
hModule Module Handle dmaChannel DMA Channel for which status is being inquired. response Place holder for whether an event is set(TRUE) or not (FALSE)
Return Value
None.
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_ER_E0;TPCC_TPCC_ER_E1;TPCC_TPCC_ER_E2;TPCC_TPCC_ER_E3; TPCC_TPCC_ER_E4;TPCC_TPCC_ER_E5;TPCC_TPCC_ER_E6;TPCC_TPCC_ER_E7; TPCC_TPCC_ER_E8;TPCC_TPCC_ER_E9;TPCC_TPCC_ER_E10;TPCC_TPCC_ER_E11; TPCC_TPCC_ER_E12;TPCC_TPCC_ER_E13;TPCC_TPCC_ER_E14;TPCC_TPCC_ER_E15; TPCC_TPCC_ER_E16;TPCC_TPCC_ER_E17;TPCC_TPCC_ER_E18;TPCC_TPCC_ER_E19; TPCC_TPCC_ER_E20;TPCC_TPCC_ER_E21;TPCC_TPCC_ER_E22;TPCC_TPCC_ER_E23; TPCC_TPCC_ER_E24;TPCC_TPCC_ER_E25;TPCC_TPCC_ER_E26;TPCC_TPCC_ER_E27; TPCC_TPCC_ER_E28;TPCC_TPCC_ER_E29;TPCC_TPCC_ER_E30;TPCC_TPCC_ER_E31;
TPCC_TPCC_ERH_E32;TPCC_TPCC_ERH_E33;TPCC_TPCC_ERH_E34;TPCC_TPCC_ERH_E35; TPCC_TPCC_ERH_E36;TPCC_TPCC_ERH_E37;TPCC_TPCC_ERH_E38;TPCC_TPCC_ERH_E39; TPCC_TPCC_ERH_E40;TPCC_TPCC_ERH_E41;TPCC_TPCC_ERH_E42;TPCC_TPCC_ERH_E43; TPCC_TPCC_ERH_E44;TPCC_TPCC_ERH_E45;TPCC_TPCC_ERH_E46;TPCC_TPCC_ERH_E47; TPCC_TPCC_ERH_E48;TPCC_TPCC_ERH_E49;TPCC_TPCC_ERH_E50;TPCC_TPCC_ERH_E51; TPCC_TPCC_ERH_E52;TPCC_TPCC_ERH_E53;TPCC_TPCC_ERH_E54;TPCC_TPCC_ERH_E55; TPCC_TPCC_ERH_E56;TPCC_TPCC_ERH_E57;TPCC_TPCC_ERH_E58;TPCC_TPCC_ERH_E59; TPCC_TPCC_ERH_E60;TPCC_TPCC_ERH_E61;TPCC_TPCC_ERH_E62;TPCC_TPCC_ERH_E63;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Bool dmaStatus; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Determine if there is an event pending on DMA Channel 0. CSL_edma3IsDMAChannelEventPending(hModule, 0, &dmaStatus); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3IsDMAChannelMissedEventSet | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel, | |||
Bool * | response | |||
) |
============================================================================
CSL_edma3IsDMAChannelMissedEventSet
Description
The API checks determines if there is a missed Event for a specific DMA channel
Arguments
hModule Module Handle dmaChannel DMA Channel to be checked response This is populated by the API and returns TRUE if the event was missed else it returns FALSE.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_EMR_EMR0;TPCC_TPCC_EMR_EMR1;TPCC_TPCC_EMR_EMR2; TPCC_TPCC_EMR_EMR3;TPCC_TPCC_EMR_EMR4;TPCC_TPCC_EMR_EMR5; TPCC_TPCC_EMR_EMR6;TPCC_TPCC_EMR_EMR7;TPCC_TPCC_EMR_EMR8; TPCC_TPCC_EMR_EMR9;TPCC_TPCC_EMR_EMR10;TPCC_TPCC_EMR_EMR11; TPCC_TPCC_EMR_EMR12;TPCC_TPCC_EMR_EMR13;TPCC_TPCC_EMR_EMR14; TPCC_TPCC_EMR_EMR15;TPCC_TPCC_EMR_EMR16;TPCC_TPCC_EMR_EMR17; TPCC_TPCC_EMR_EMR18;TPCC_TPCC_EMR_EMR19;TPCC_TPCC_EMR_EMR20; TPCC_TPCC_EMR_EMR21;TPCC_TPCC_EMR_EMR22;TPCC_TPCC_EMR_EMR23; TPCC_TPCC_EMR_EMR24;TPCC_TPCC_EMR_EMR25;TPCC_TPCC_EMR_EMR26; TPCC_TPCC_EMR_EMR27;TPCC_TPCC_EMR_EMR28;TPCC_TPCC_EMR_EMR29; TPCC_TPCC_EMR_EMR30;TPCC_TPCC_EMR_EMR31; TPCC_TPCC_EMRH_EMR32;TPCC_TPCC_EMRH_EMR33;TPCC_TPCC_EMRH_EMR34; TPCC_TPCC_EMRH_EMR35;TPCC_TPCC_EMRH_EMR36;TPCC_TPCC_EMRH_EMR37; TPCC_TPCC_EMRH_EMR38;TPCC_TPCC_EMRH_EMR39;TPCC_TPCC_EMRH_EMR40; TPCC_TPCC_EMRH_EMR41;TPCC_TPCC_EMRH_EMR42;TPCC_TPCC_EMRH_EMR43; TPCC_TPCC_EMRH_EMR44;TPCC_TPCC_EMRH_EMR45;TPCC_TPCC_EMRH_EMR46; TPCC_TPCC_EMRH_EMR47;TPCC_TPCC_EMRH_EMR48;TPCC_TPCC_EMRH_EMR49; TPCC_TPCC_EMRH_EMR50;TPCC_TPCC_EMRH_EMR51;TPCC_TPCC_EMRH_EMR52; TPCC_TPCC_EMRH_EMR53;TPCC_TPCC_EMRH_EMR54;TPCC_TPCC_EMRH_EMR55; TPCC_TPCC_EMRH_EMR56;TPCC_TPCC_EMRH_EMR57;TPCC_TPCC_EMRH_EMR58; TPCC_TPCC_EMRH_EMR59;TPCC_TPCC_EMRH_EMR60;TPCC_TPCC_EMRH_EMR61; TPCC_TPCC_EMRH_EMR62;TPCC_TPCC_EMRH_EMR63;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Bool missed; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Check if DMA Channel 1 has an event missed. CSL_edma3IsDMAChannelMissedEventSet(hModule, 1, &missed); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3IsDMAChannelSecondaryEventSet | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel, | |||
Bool * | response | |||
) |
============================================================================
CSL_edma3IsDMAChannelSecondaryEventSet
Description
This API is used to determine if the secondary Event for a specific DMA channel is set or not?
Arguments
hModule Module Handle dmaChannel DMA Channel for which secondary Events are being checked response Status of the check populated by the API (TRUE if event is missed else FALSE)
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_SER_SER0;TPCC_TPCC_SER_SER1;TPCC_TPCC_SER_SER2; TPCC_TPCC_SER_SER3;TPCC_TPCC_SER_SER4;TPCC_TPCC_SER_SER5; TPCC_TPCC_SER_SER6;TPCC_TPCC_SER_SER7;TPCC_TPCC_SER_SER8; TPCC_TPCC_SER_SER9;TPCC_TPCC_SER_SER10;TPCC_TPCC_SER_SER11; TPCC_TPCC_SER_SER12;TPCC_TPCC_SER_SER13;TPCC_TPCC_SER_SER14; TPCC_TPCC_SER_SER15;TPCC_TPCC_SER_SER16;TPCC_TPCC_SER_SER17; TPCC_TPCC_SER_SER18;TPCC_TPCC_SER_SER19;TPCC_TPCC_SER_SER20; TPCC_TPCC_SER_SER21;TPCC_TPCC_SER_SER22;TPCC_TPCC_SER_SER23; TPCC_TPCC_SER_SER24;TPCC_TPCC_SER_SER25;TPCC_TPCC_SER_SER26; TPCC_TPCC_SER_SER27;TPCC_TPCC_SER_SER28;TPCC_TPCC_SER_SER29; TPCC_TPCC_SER_SER30;TPCC_TPCC_SER_SER31;
TPCC_TPCC_SERH_SER32;TPCC_TPCC_SERH_SER33;TPCC_TPCC_SERH_SER34; TPCC_TPCC_SERH_SER35;TPCC_TPCC_SERH_SER36;TPCC_TPCC_SERH_SER37; TPCC_TPCC_SERH_SER38;TPCC_TPCC_SERH_SER39;TPCC_TPCC_SERH_SER40; TPCC_TPCC_SERH_SER41;TPCC_TPCC_SERH_SER42;TPCC_TPCC_SERH_SER43; TPCC_TPCC_SERH_SER44;TPCC_TPCC_SERH_SER45;TPCC_TPCC_SERH_SER46; TPCC_TPCC_SERH_SER47;TPCC_TPCC_SERH_SER48;TPCC_TPCC_SERH_SER49; TPCC_TPCC_SERH_SER50;TPCC_TPCC_SERH_SER51;TPCC_TPCC_SERH_SER52; TPCC_TPCC_SERH_SER53;TPCC_TPCC_SERH_SER54;TPCC_TPCC_SERH_SER55; TPCC_TPCC_SERH_SER56;TPCC_TPCC_SERH_SER57;TPCC_TPCC_SERH_SER58; TPCC_TPCC_SERH_SER59;TPCC_TPCC_SERH_SER60;TPCC_TPCC_SERH_SER61; TPCC_TPCC_SERH_SER62;TPCC_TPCC_SERH_SER63;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Bool response; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Check if the DMA Channel 1 Secondary Event is set or not? CSL_edma3IsDMAChannelSecondaryEventSet(hModule, 1, &response); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3IsQDMAChannelEventPending | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel, | |||
Bool * | response | |||
) |
============================================================================
CSL_edma3IsQDMAChannelEventPending
Description
The function gets the status of the specified QDMA channel i.e. if there is a pending event on the specific channel.
Arguments
hModule Module Handle qdmaChannel QDMA Channel for which status is being inquired. response Place holder for whether an event is set(TRUE) or not (FALSE)
Return Value
None.
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QER_QER0;TPCC_TPCC_QER_QER1;TPCC_TPCC_QER_QER2;TPCC_TPCC_QER_QER3; TPCC_TPCC_QER_QER4;TPCC_TPCC_QER_QER5;TPCC_TPCC_QER_QER6;TPCC_TPCC_QER_QER7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Bool qdmaStatus; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Is QDMA Channel 1 event pending. CSL_edma3IsQDMAChannelEventPending(hModule, 1, &qdmaStatus); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3IsQDMAChannelMissedEventSet | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel, | |||
Bool * | response | |||
) |
============================================================================
CSL_edma3IsQDMAChannelMissedEventSet
Description
The API checks determines if there is a missed Event for a specific DMA channel
Arguments
hModule Module Handle qdmaChannel QDMA Channel to be checked response This is populated by the API and returns TRUE if the event was missed else it returns FALSE.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QEMR_QEMR0;TPCC_TPCC_QEMR_QEMR1;TPCC_TPCC_QEMR_QEMR2; TPCC_TPCC_QEMR_QEMR3;TPCC_TPCC_QEMR_QEMR4;TPCC_TPCC_QEMR_QEMR5; TPCC_TPCC_QEMR_QEMR6;TPCC_TPCC_QEMR_QEMR7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Bool missed; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Check if DMA Channel 0 has an event missed. CSL_edma3IsQDMAChannelMissedEventSet(hModule, 0, &missed); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3IsQDMAChannelSecondaryEventSet | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel, | |||
Bool * | response | |||
) |
============================================================================
CSL_edma3IsDMAChannelSecondaryEventSet
Description
This API is used to determine if the secondary Event for a specific DMA channel is set or not?
Arguments
hModule Module Handle qdmaChannel QDMA Channel for which secondary Events are being checked response Status of the check populated by the API (TRUE if event is missed else FALSE)
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Reads
TPCC_TPCC_QSER_QSER0;TPCC_TPCC_QSER_QSER1;TPCC_TPCC_QSER_QSER2; TPCC_TPCC_QSER_QSER3;TPCC_TPCC_QSER_QSER4;TPCC_TPCC_QSER_QSER5; TPCC_TPCC_QSER_QSER6;TPCC_TPCC_QSER_QSER7;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; Bool response; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Check if the QDMA Channel 1 Secondary Event is set or not? CSL_edma3IsQDMAChannelSecondaryEventSet(hModule, 1, &response); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3MapDMAChannelToEventQueue | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel, | |||
Uint8 | eventQueue | |||
) |
============================================================================
CSL_edma3MapDMAChannelToEventQueue
Description
The function maps the event ID to the specific DMA Queue.
Arguments
hModule Module Handle dmaChannel DMA Channel to which the event is mapped. eventQueue Event Queue which is to be mapped.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
DMA Channel is mapped to the specified Event Queue.
Writes
TPCC_TPCC_DMAQNUM_E0;TPCC_TPCC_DMAQNUM_E1;TPCC_TPCC_DMAQNUM_E2; TPCC_TPCC_DMAQNUM_E3;TPCC_TPCC_DMAQNUM_E4;TPCC_TPCC_DMAQNUM_E5; TPCC_TPCC_DMAQNUM_E6;TPCC_TPCC_DMAQNUM_E7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Maps DMA Channel 1 to Event Queue 2 CSL_edma3MapDMAChannelToEventQueue(hModule, 1, 2); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3MapDMAChannelToParamBlock | ( | CSL_Edma3Handle | hModule, | |
Uint8 | dmaChannel, | |||
Uint16 | paramId | |||
) |
============================================================================
CSL_edma3MapDMAChannelToParamBlock
Description
The function maps the DMA Channel to the specified PARAM Entry Block.
Arguments
hModule Module Handle dmaChannel DMA Channel Number which is to be mapped. paramId Parameter Identifier to be mapped to.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
DMA Channel is mapped to the specified PARAM Block.
Writes
TPCC_TPCC_DCHMAP_PAENTRY
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Maps DMA Channel 1 to Param ID Block 5. CSL_edma3MapDMAChannelToParamBlock(hModule, 1, 5); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3MapEventQueueToTC | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue, | |||
Uint8 | tcNum | |||
) |
============================================================================
CSL_edma3MapEventQueueToTC
Description
The function maps the event queue to a specific TC
Arguments
hModule Module Handle eventQueue Event Queue which is to be mapped. tcNum TC to which the queue is to be mapped to.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
Event Queue is mapped to the specific TC
Writes
TPCC_TPCC_QUETCMAP_TCNUMQ0;TPCC_TPCC_QUETCMAP_TCNUMQ1;TPCC_TPCC_QUETCMAP_TCNUMQ2; TPCC_TPCC_QUETCMAP_TCNUMQ3;TPCC_TPCC_QUETCMAP_TCNUMQ4;TPCC_TPCC_QUETCMAP_TCNUMQ5; TPCC_TPCC_QUETCMAP_TCNUMQ6;TPCC_TPCC_QUETCMAP_TCNUMQ7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Maps Event Queue 1 to TC0 CSL_edma3MapEventQueueToTC(hModule, 1, 0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3MapQDMAChannelToEventQueue | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel, | |||
Uint8 | eventQueue | |||
) |
============================================================================
CSL_edma3MapQDMAChannelToEventQueue
Description
The function maps the event ID to the specific DMA Queue.
Arguments
hModule Module Handle qdmaChannel QDMA Channel to which the event is mapped. eventQueue Event Queue which is to be mapped.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
DMA Channel is mapped to the specified Event Queue.
Writes
TPCC_TPCC_QDMAQNUM_E0;TPCC_TPCC_QDMAQNUM_E1;TPCC_TPCC_QDMAQNUM_E2; TPCC_TPCC_QDMAQNUM_E3;TPCC_TPCC_QDMAQNUM_E4;TPCC_TPCC_QDMAQNUM_E5; TPCC_TPCC_QDMAQNUM_E6;TPCC_TPCC_QDMAQNUM_E7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Maps QDMA Channel 1 to Event Queue 2 CSL_edma3MapQDMAChannelToEventQueue(hModule, 1, 2); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3MapQDMAChannelToParamBlock | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel, | |||
Uint16 | paramId | |||
) |
============================================================================
CSL_edma3MapQDMAChannelToParamBlock
Description
The function maps the QDMA Channel to the specified PARAM Entry Block.
Arguments
hModule Module Handle qdmaChannel QDMA Channel Number which is to be mapped. paramId Parameter Identifier to be mapped to.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
QDMA Channel is mapped to the specified PARAM Block.
Writes
TPCC_TPCC_QCHMAP_PAENTRY
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Maps QDMA Channel 1 to Param ID Block 5. CSL_edma3MapQDMAChannelToParamBlock(hModule, 1, 5); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3MemFaultClear | ( | CSL_Edma3Handle | hModule | ) |
============================================================================
CSL_edma3MemFaultClear
Description
The function clears the memory fault.
Arguments
hModule Module Handle
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_MPFCR_MPFCLR=1
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Clear the memory protection fault CSL_edma3MemFaultClear(hModule); ...
===========================================================================
CSL_Edma3Handle CSL_edma3Open | ( | CSL_Edma3Obj * | pEdmaObj, | |
CSL_InstNum | edmaNum, | |||
CSL_Edma3ModuleAttr * | pAttr, | |||
CSL_Status * | pStatus | |||
) |
============================================================================
CSL_edma3Open
Description
This function returns the handle to the EDMA instance. This handle is passed to all other CSL APIs.
Arguments
pEdmaObj EDMA Module Object pointer edmaNum Instance of EDMA pAttr EDMA Attribute pointer pStatus Status of the function call
Return Value
Success - Valid Edma handle will be returned if status value is equal to CSL_SOK.
Failure - NULL
Pre Condition
The EDMA must be succesfully initialized via CSL_edma3Init() before calling this function.
Post Condition
1. The status is returned in the status variable. If status returned is
2. Edma object structure is populated
Affects
None
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
=============================================================================
CSL_Status CSL_edma3ParamSetup | ( | CSL_Edma3ParamHandle | hParamHndl, | |
CSL_Edma3ParamSetup * | setup | |||
) |
============================================================================
CSL_edma3ParamSetup
Description
The function is used to configure the PARAM Entry block with the specific parameter information.
Arguments
hParamHndl Handle to the param entry setup Pointer to param setup structure
Return Value
Success - CSL_SOK
Error - CSL_ESYS_BADHANDLE (The handle passed is invalid)
Error - CSL_ESYS_INVPARAMS (The parameter passed is invalid)
Pre Condition
CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be called successfully in that order before this API can be invoked
Post Condition
Configures the EDMA parameter Entry
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3ParamHandle hParamBasic; CSL_Edma3ParamSetup myParamSetup; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Open DMA Channel 1. chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL; chAttr.chaNum = 1; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); if ((hChannel == NULL) || (status != CSL_SOK)) { printf ("Error: Unable to open EDMA Channel:%d\n", channelNum); return -1; } ... // Obtain a handle to PARAM Entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); ... // Setup the first param Entry (Ping buffer) myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \ CSL_EDMA3_TCCH_DIS, \ CSL_EDMA3_ITCINT_DIS, \ CSL_EDMA3_TCINT_EN,\ 0,CSL_EDMA3_TCC_NORMAL,\ CSL_EDMA3_FIFOWIDTH_NONE, \ CSL_EDMA3_STATIC_DIS, \ CSL_EDMA3_SYNC_A, \ CSL_EDMA3_ADDRMODE_INCR, \ CSL_EDMA3_ADDRMODE_INCR); myParamSetup.srcAddr = (Uint32)srcBuff1; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1); myParamSetup.dstAddr = (Uint32)dstBuff1; myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1); myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0); myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1); myParamSetup.cCnt = 1; // Configure the PARAM Entry with the setup information. CSL_edma3ParamSetup(hParamBasic,&myParamSetup); ...
=============================================================================
CSL_Status CSL_edma3ParamWriteWord | ( | CSL_Edma3ParamHandle | hParamHndl, | |
Uint16 | wordOffset, | |||
Uint32 | word | |||
) |
============================================================================
CSL_edma3ParamWriteWord
Description
This is for the ease of QDMA channels. Once the QDMA channel transfer is triggered, subsequent triggers may be done with only writing the modified words in the parameter entry along with the trigger word. This API is expected to achieve this purpose. Most usage scenarios, the user should not be writing more than the trigger word entry.
Arguments
hParamHndl Handle to the param entry wordOffset word offset in the 8 word paramater entry word word to be written
Return Value
Success - CSL_SOK (Param Write Word successful)
Error - CSL_ESYS_BADHANDLE (Invalid handle)
Pre Condition
CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() and must be CSL_edma3GetParamHandle(), CSL_edma3ParamSetup() called successfully in that order before this API can be invoked. The main setup structure consists of pointers to sub-structures.The user has to allocate space for & fill in the parameter setup structure.
Post Condition
Configure trigger word
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Status status; CSL_Edma3ChannelHandle hChannel; CSL_Edma3ChannelAttr chAttr; CSL_Edma3ParamHandle hParamBasic; // Module Initialization CSL_edma3Init(NULL); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Open DMA Channel 1. chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL; chAttr.chaNum = 1; hChannel = CSL_edma3ChannelOpen(&chObj, 0, &chAttr, &status); if ((hChannel == NULL) || (status != CSL_SOK)) { printf ("Error: Unable to open EDMA Channel:%d\n", channelNum); return -1; } ... // Obtain a handle to PARAM Entry 0 hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status); ... // Write trigger word CSL_edma3ParamWriteWord(hParamBasic, 7, myParamSetup.cCnt); ...
=============================================================================
CSL_IDEF_INLINE void CSL_edma3QDMAChannelDisable | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
Uint8 | qdmaChannel | |||
) |
============================================================================
CSL_edma3QDMAChannelDisable
Description
This API disables the specified QDMA Channel.
Arguments
hModule Module Handle region Region (Shadown Region or Global) qdmaChannel QDMA Channel to be disabled.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_QEECR_QEECR0=1;TPCC_TPCC_QEECR_QEECR1=1;TPCC_TPCC_QEECR_QEECR2=1; TPCC_TPCC_QEECR_QEECR3=1;TPCC_TPCC_QEECR_QEECR4=1;TPCC_TPCC_QEECR_QEECR5=1; TPCC_TPCC_QEECR_QEECR6=1;TPCC_TPCC_QEECR_QEECR7=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Disables QDMA Channel 0 CSL_edma3QDMAChannelDisable(hModule, 0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3QDMAChannelEnable | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
Uint8 | qdmaChannel | |||
) |
============================================================================
CSL_edma3QDMAChannelEnable
Description
This API enables the specified QDMA Channel.
Arguments
hModule Module Handle region Region (Shadown Region or Global) qdmaChannel QDMA Channel to be enabled.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_QEESR_QEESR0=1;TPCC_TPCC_QEESR_QEESR1=1;TPCC_TPCC_QEESR_QEESR2=1; TPCC_TPCC_QEESR_QEESR3=1;TPCC_TPCC_QEESR_QEESR4=1;TPCC_TPCC_QEESR_QEESR5=1; TPCC_TPCC_QEESR_QEESR6=1;TPCC_TPCC_QEESR_QEESR7=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Enables QDMA Channel 1 for Global Region. CSL_edma3QDMAChannelEnable(hModule, CSL_EDMA3_REGION_GLOBAL, 1); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3QdmaRegionAccessDisable | ( | CSL_Edma3Handle | hModule, | |
Int | edmaRegion, | |||
CSL_BitMask32 | qrae | |||
) |
============================================================================
CSL_edma3QdmaRegionAccessDisable
Description
This API disables read/write access to the shadow regions for the specific QDMA channels.
Arguments
hModule Module Handle edmaRegion Shadow Region. qrae Bitmask to be enabled in QRAE
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_QRAE_E0=0;TPCC_TPCC_QRAE_E1=0;TPCC_TPCC_QRAE_E2=0; TPCC_TPCC_QRAE_E3=0;TPCC_TPCC_QRAE_E4=0;TPCC_TPCC_QRAE_E5=0; TPCC_TPCC_QRAE_E6=0;TPCC_TPCC_QRAE_E7=0
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Disable read/write access in Region 0 for QDMA 0 to 3 CSL_edma3QdmaRegionAccessDisable(hModule, 0, 0x0000000F); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3QdmaRegionAccessEnable | ( | CSL_Edma3Handle | hModule, | |
Int | edmaRegion, | |||
CSL_BitMask32 | qrae | |||
) |
============================================================================
CSL_edma3QdmaRegionAccessEnable
Description
This API enables read/write access to the shadow regions for the specific QDMA channels.
Arguments
hModule Module Handle edmaRegion Shadow Region qrae Bitmask to be enabled in QRAE
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_QRAE_E0=1;TPCC_TPCC_QRAE_E1=1;TPCC_TPCC_QRAE_E2=1; TPCC_TPCC_QRAE_E3=1;TPCC_TPCC_QRAE_E4=1;TPCC_TPCC_QRAE_E5=1; TPCC_TPCC_QRAE_E6=1;TPCC_TPCC_QRAE_E7=1
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); // Enable read/write access in Region 0 for QDMA 0 to 3 CSL_edma3QdmaRegionAccessEnable(hModule, 0, 0x0000000F);
===========================================================================
CSL_IDEF_INLINE void CSL_edma3SetDMAChannelEvent | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
Uint8 | dmaChannel | |||
) |
============================================================================
CSL_edma3SetDMAChannelEvent
Description
This API sets the event for the specific DMA channel.
Arguments
hModule Module Handle region Region (Shadow or Global) dmaChannel DMA Channel for which the event is to be set
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_ESR_E0=1;TPCC_TPCC_ESR_E1=1;TPCC_TPCC_ESR_E2=1;TPCC_TPCC_ESR_E3=1; TPCC_TPCC_ESR_E4=1;TPCC_TPCC_ESR_E5=1;TPCC_TPCC_ESR_E6=1;TPCC_TPCC_ESR_E7=1; TPCC_TPCC_ESR_E8=1;TPCC_TPCC_ESR_E9=1;TPCC_TPCC_ESR_E10=1;TPCC_TPCC_ESR_E11=1; TPCC_TPCC_ESR_E12=1;TPCC_TPCC_ESR_E13=1;TPCC_TPCC_ESR_E14=1;TPCC_TPCC_ESR_E15=1; TPCC_TPCC_ESR_E16=1;TPCC_TPCC_ESR_E17=1;TPCC_TPCC_ESR_E18=1;TPCC_TPCC_ESR_E19=1; TPCC_TPCC_ESR_E20=1;TPCC_TPCC_ESR_E21=1;TPCC_TPCC_ESR_E22=1;TPCC_TPCC_ESR_E23=1; TPCC_TPCC_ESR_E24=1;TPCC_TPCC_ESR_E25=1;TPCC_TPCC_ESR_E26=1;TPCC_TPCC_ESR_E27=1; TPCC_TPCC_ESR_E28=1;TPCC_TPCC_ESR_E29=1;TPCC_TPCC_ESR_E30=1;TPCC_TPCC_ESR_E31=1;
TPCC_TPCC_ESRH_E32=1;TPCC_TPCC_ESRH_E33=1;TPCC_TPCC_ESRH_E34=1;TPCC_TPCC_ESRH_E35=1; TPCC_TPCC_ESRH_E36=1;TPCC_TPCC_ESRH_E37=1;TPCC_TPCC_ESRH_E38=1;TPCC_TPCC_ESRH_E39=1; TPCC_TPCC_ESRH_E40=1;TPCC_TPCC_ESRH_E41=1;TPCC_TPCC_ESRH_E42=1;TPCC_TPCC_ESRH_E43=1; TPCC_TPCC_ESRH_E44=1;TPCC_TPCC_ESRH_E45=1;TPCC_TPCC_ESRH_E46=1;TPCC_TPCC_ESRH_E47=1; TPCC_TPCC_ESRH_E48=1;TPCC_TPCC_ESRH_E49=1;TPCC_TPCC_ESRH_E50=1;TPCC_TPCC_ESRH_E51=1; TPCC_TPCC_ESRH_E52=1;TPCC_TPCC_ESRH_E53=1;TPCC_TPCC_ESRH_E54=1;TPCC_TPCC_ESRH_E55=1; TPCC_TPCC_ESRH_E56=1;TPCC_TPCC_ESRH_E57=1;TPCC_TPCC_ESRH_E58=1;TPCC_TPCC_ESRH_E59=1; TPCC_TPCC_ESRH_E60=1;TPCC_TPCC_ESRH_E61=1;TPCC_TPCC_ESRH_E62=1;TPCC_TPCC_ESRH_E63=1;
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Set the DMA Channel 0 Event for the Global Region. CSL_edma3SetDMAChannelEvent(hModule, CSL_EDMA3_REGION_GLOBAL, 0); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3SetEventQueuePriority | ( | CSL_Edma3Handle | hModule, | |
Uint8 | eventQueue, | |||
Uint8 | priority | |||
) |
============================================================================
CSL_edma3SetEventQueuePriority
Description
The function sets the priority of the specific event queue.
Arguments
hModule Module Handle eventQueue Event Queue whose priority is to be configured. priority Priority to be configured.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
Event Queue is configured to the specific priority.
Writes
TPCC_TPCC_QUEPRI_PRIQ0;TPCC_TPCC_QUEPRI_PRIQ1;TPCC_TPCC_QUEPRI_PRIQ2; TPCC_TPCC_QUEPRI_PRIQ3;TPCC_TPCC_QUEPRI_PRIQ4;TPCC_TPCC_QUEPRI_PRIQ5; TPCC_TPCC_QUEPRI_PRIQ6;TPCC_TPCC_QUEPRI_PRIQ7
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Maps Event Queue 2 to Priority 4 CSL_edma3SetEventQueuePriority(hModule, 2, 4); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3SetMemoryProtectionAttrib | ( | CSL_Edma3Handle | hModule, | |
Int | region, | |||
CSL_BitMask32 | mppa | |||
) |
============================================================================
CSL_edma3SetMemoryProtectionAttrib
Description
This API sets the memory protection attributes for the specified region.
Arguments
hModule Module Handle region Region being configured. mpa Value to be programmed into the MPPAG/MPPA[0/1/2/../n] This is a Bitmask of the protection attributes.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
None
Writes
TPCC_TPCC_MPPAG;TPCC_TPCC_MPPA
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status); ... // Set the memory protection attributes of region 0. CSL_edma3SetMemoryProtectionAttrib (hModule, 0, CSL_EDMA3_MEMACCESS_UX | CSL_EDMA3_MEMACCESS_UW | CSL_EDMA3_MEMACCESS_UR | CSL_EDMA3_MEMACCESS_AID2)); ...
===========================================================================
CSL_IDEF_INLINE void CSL_edma3SetQDMATriggerWord | ( | CSL_Edma3Handle | hModule, | |
Uint8 | qdmaChannel, | |||
Uint8 | trword | |||
) |
============================================================================
CSL_edma3SetQDMATriggerWord
Description
The function sets the trigger word of the PaRAM Entry block.
Arguments
hModule Module Handle qdmaChannel QDMA Channel Number which is to be configured. trword Trigger Word to be configured.
Return Value
None
Pre Condition
Both CSL_edma3Init() and CSL_edma3Open() must be called.
Post Condition
QDMA Channel is mapped to the specified PARAM Block.
Writes
TPCC_TPCC_QCHMAP_TRWORD
Example
CSL_Edma3Handle hModule; CSL_Edma3Obj edmaObj; CSL_Edma3Context context; CSL_Status status; // Module Initialization CSL_edma3Init(&context); // Module Level Open hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status); // Configure QDMA Channel 1 Trigger Word as 0 CSL_edma3SetQDMATriggerWord(hModule, 1, 0); ...
===========================================================================