Data Structures

Here are the data structures with brief descriptions:
CSL_BWMNGMT_CPUARB_SETUPCSL_BWMNGMT_CPUARB_SETUP has all the fields required to configure the CPU Arbitration Control Register of BWMNGMT for any given memory control block (L1D/L2/EMC)
CSL_BWMNGMT_MDMAPRI_SETUPCSL_BWMNGMT_MDMAPRI_SETUP has all the fields required to configure Master DMA (MDMA) Arbitration Control Register of BWMNGMT for L2/UMC memory control block
CSL_CPGMAC_SL_MACSTATUSHolds MAC status register contents
CSL_CPGMAC_SL_VERSIONHolds the Sliver submodule's version info
CSL_CPSW_3GF_ALE_MCASTADDR_ENTRYHolds the ALE Multicast Address Table entry configuration
CSL_CPSW_3GF_ALE_OUIADDR_ENTRYHolds the ALE OUI Unicast Address Table entry configuration
CSL_CPSW_3GF_ALE_PORTCONTROLHolds the ALE Port control register info
CSL_CPSW_3GF_ALE_UNICASTADDR_ENTRYHolds the ALE Unicast Address Table entry configuration
CSL_CPSW_3GF_ALE_VERSIONHolds the ALE submodule's version info
CSL_CPSW_3GF_ALE_VLAN_ENTRYHolds the ALE VLAN Table entry configuration
CSL_CPSW_3GF_ALE_VLANMCASTADDR_ENTRYHolds the ALE VLAN/Multicast Address Table entry configuration
CSL_CPSW_3GF_ALE_VLANUNICASTADDR_ENTRYHolds the ALE VLAN Unicast Address Table entry configuration
CSL_CPSW_3GF_CONTROLHolds CPSW control register contents
CSL_CPSW_3GF_FLOWCNTLHolds flow control register contents
CSL_CPSW_3GF_PORTSTATHolds Port Statistics Enable register contents
CSL_CPSW_3GF_PTYPEHolds Priority type register contents
CSL_CPSW_3GF_STATSHolds the EMAC statistics
CSL_CPSW_3GF_TSCNTLHolds Port Time Sync Control register contents
CSL_CPSW_3GF_VERSIONHolds the Time sync submodule's version info
CSL_CPSW_3GFSS_VERSIONHolds the Ethernet switch subsystem's version info
CSL_CPTS_EVENTINFOHolds Time sync event info contents
CSL_CPTS_VERSIONHolds the Time sync submodule's version info
CSL_Edma3ActivityStatEdma Channel Controller Activity Status
CSL_Edma3CfgInfoEDMA3 Configuration Information This describes the configuration information for each EDMA instance. This is populated by the SOC layer for each instance
CSL_Edma3ChannelAttrEdma Channel parameter structure used for opening a channel
CSL_Edma3ChannelErrEdma Channel Error
CSL_Edma3ChannelObjEdma Object Structure
CSL_Edma3CmdDraeEdma Command Structure for setting region specific attributes
CSL_Edma3CmdIntrEdma Control/Query Control Command structure for issuing commands for Interrupt related APIs An object of this type is allocated by the user and its address is passed to the Control API
CSL_Edma3CmdQraeEdma Control/Query Command Structure for querying qdma region access enable attributes
CSL_Edma3CmdQuePriEdma Command Structure used for setting Event Que priority level
CSL_Edma3CmdQueThrEdma Command Structure used for setting Event Que threshold level
CSL_Edma3CmdRegionEdma Control/Query Command Structure for querying region specific attributes
CSL_Edma3CtrlErrStatEdma Controller Error Status
CSL_Edma3HwDmaChannelSetupQDMA Edma Channel Setup
CSL_Edma3HwQdmaChannelSetupQDMA Edma Channel Setup
CSL_Edma3HwSetupEdma Hw Setup Structure
CSL_Edma3MemFaultStatEdma Memory Protection Fault Error Status
CSL_Edma3ModuleBaseAddressThis will have the base-address information for the module instance
CSL_Edma3ObjThis object contains the reference to the instance of Edma Module opened using the CSL_edma3Open()
CSL_Edma3ParamSetupEdma ParamSetup Structure
CSL_Edma3QueryInfoEdma Controller Information
CSL_Edma3QueStatEdma Controller Que Status
CSL_IDMA_IDMA0CONFIGThis structure holds the information required to initiate a iDMA Channel 0 Configuration(CFG) space Transfer request from the GEM
CSL_IDMA_IDMA1CONFIGThis structure holds the information required to initiate a iDMA Channel 1 Block Fill/Transfer request in the GEM
CSL_IDMA_STATUSThis structure holds the information required to interpret the IDMA Channel 0/1 Transfer Status
CSL_IntcContext
CSL_IntcDropStatus
CSL_IntcEventHandlerRecord
CSL_IntcObj
CSL_MDIO_USERACCESSHolds the MDIO User Access Register contents
CSL_MDIO_USERPHYSELHolds the MDIO User Phy Select Register contents
CSL_MDIO_VERSIONHolds the MDIO peripheral's version info
CSL_MEMPROT_MPFSRThis will be used to query the memory fault status
CSL_MEMPROT_MPLKSTATThis will be used to lock/unlock/reset a memory region
CSL_MEMPROT_MPPAThis will be used to set/query the memory page attributes
CSL_SGMII_ADVABILITYSGMII advertised ability configuration info
CSL_SGMII_STATUSHolds the SGMII status info
CSL_SGMII_VERSIONHolds the SGMII module version info
CSL_TmrBaseAddressThis structure contains the base-address information for the peripheral instance
CSL_TmrConfigConfig-structure Used to configure the GP timer using CSL_tmrHwSetupRaw()
CSL_TmrContextModule specific context information. Present implementation of GP timer CSL doesn't have any context information
CSL_TmrHwSetupHardware setup structure
CSL_TmrObjWatchdog timer object structure
CSL_TmrParamModule specific parameters. Present implementation of GP timer CSL doesn't have any module specific parameters
CSL_XMC_MPFSRThis is the definition of CSL_XMC_MPFSR
CSL_XMC_XMPAXHThis is the definition of CSL_XMC_XMPAXH
CSL_XMC_XMPAXLThis is the definition of CSL_XMC_XMPAXL
CSL_XMC_XPFADDRThis is the definition of CSL_XMC_XPFADDR
EMIF4_ECC_CONTROLECC Control
EMIF4_MSTID_COS_MAPPINGMaster ID to COS Mapping
EMIF4_PRI_COS_MAPPINGPriority to COS Mapping
EMIF4F_IODFT_CONTROLIODFT Control Values
EMIF4F_LPDDR2NVM_TIMING_CONFIGLPDDR2-NVM Timing Configuration
EMIF4F_OUTPUT_IMP_CONFIGSDRAM Output Impedance Calibration Configuation
EMIF4F_PERF_CONFIGPerformance Counter Configuration
EMIF4F_PWR_MGMT_CONFIGPower Management Configuration
EMIF4F_SDRAM_CONFIGEMIF4F SDRAM Configuration
EMIF4F_TEMP_ALERT_CONFIGTemperature Alert Configuration
EMIF4F_TIMING1_CONFIGEMIF4F Timing1 Configuration
EMIF4F_TIMING2_CONFIGEMIF4F Timing2 Configuration
EMIF4F_TIMING3_CONFIGEMIF4F Timing3 Configuration
EMIF4F_VBUS_CONFIG_VALUEVBUS Configuration Values
SRIO_AMU_PANESRIO AMU Pane
SRIO_AMU_WINDOWSRIO AMU Window
SRIO_ERR_RATESRIO Error Rate
SRIO_LANE_STATUSSRIO Lane Status
SRIO_LSU_TRANSFERSRIO LSU Transfer
SRIO_MESSAGESRIO Message Description
SRIO_OP_CARSRIO Operation Capability Register
SRIO_PE_FEATURESSRIO Processing Element Features
SRIO_PLM_CONTROL_SYMBOLSRIO PLM Control Symbol Configuration
SRIO_PLM_IMPL_CONTROLSRIO Lane Status
SRIO_PLM_POLARITY_CONTROLSRIO PLM Polarity Control
SRIO_PLM_VMIN_EXPONENTSRIO PLM VMin Exponent
SRIO_TLM_CONTROLSRIO TLM Control Configuration
SRIO_TYPE9_MESSAGESRIO Type 9 Message Description

Copyright 2012, Texas Instruments Incorporated