TIMER Enumerated Data Types
[TIMER]

Enumerations

enum  CSL_TmrHwControlCmd {
  CSL_TMR_CMD_LOAD_PRDLO = 0, CSL_TMR_CMD_LOAD_PRDHI = 1, CSL_TMR_CMD_LOAD_PSCHI = 2, CSL_TMR_CMD_START_TIMLO = 3,
  CSL_TMR_CMD_START_TIMHI = 4, CSL_TMR_CMD_STOP_TIMLO = 5, CSL_TMR_CMD_STOP_TIMHI = 6, CSL_TMR_CMD_RESET_TIMLO = 7,
  CSL_TMR_CMD_RESET_TIMHI = 8, CSL_TMR_CMD_START64 = 9, CSL_TMR_CMD_STOP64 = 10, CSL_TMR_CMD_RESET64 = 11,
  CSL_TMR_CMD_START_WDT = 12, CSL_TMR_CMD_LOAD_WDKEY = 13
}
 

This enum describes the commands used to control the GP timer through CSL_tmrHwControl().

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enum  CSL_TmrHwStatusQuery {
  CSL_TMR_QUERY_COUNT_LO = 0, CSL_TMR_QUERY_COUNT_HI = 1, CSL_TMR_QUERY_TSTAT_LO = 2, CSL_TMR_QUERY_TSTAT_HI = 3,
  CSL_TMR_QUERY_WDFLAG_STATUS = 4
}
 

This enum describes the commands used to get status of various parameters of the GP timer. These values are used in CSL_tmrGetHwStatus().

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enum  CSL_TmrIpGate { CSL_TMR_CLOCK_INP_NOGATE = 0, CSL_TMR_CLOCK_INP_GATE = 1 }
 

This enum describes whether the Timer Clock input is gated or not gated.

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enum  CSL_TmrClksrc { CSL_TMR_CLKSRC_INTERNAL = 0, CSL_TMR_CLKSRC_TMRINP = 1 }
 

This enum describes the Timer Clock source selection.

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enum  CSL_TmrEnamode { CSL_TMR_ENAMODE_DISABLE = 0, CSL_TMR_ENAMODE_ENABLE = 1, CSL_TMR_ENAMODE_CONT = 2 }
 

This enum describes the enabling/disabling of Timer.

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enum  CSL_TmrPulseWidth { CSL_TMR_PWID_ONECLK = 0, CSL_TMR_PWID_TWOCLKS = 1, CSL_TMR_PWID_THREECLKS = 2, CSL_TMR_PWID_FOURCLKS = 3 }
 

This enum describes the Timer Clock cycles (1/2/3/4).

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enum  CSL_TmrClockPulse { CSL_TMR_CP_PULSE = 0, CSL_TMR_CP_CLOCK = 1 }
 

This enum describes the mode of Timer Clock (Pulse/Clock).

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enum  CSL_TmrInvInp { CSL_TMR_INVINP_UNINVERTED = 0, CSL_TMR_INVINP_INVERTED = 1 }
 

This enum describes the Timer input inverter control.

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enum  CSL_TmrInvOutp { CSL_TMR_INVOUTP_UNINVERTED = 0, CSL_TMR_INVOUTP_INVERTED = 1 }
 

This enum describes the Timer output inverter control.

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enum  CSL_TmrMode { CSL_TMR_TIMMODE_GPT = 0, CSL_TMR_TIMMODE_DUAL_UNCHAINED = 1, CSL_TMR_TIMMODE_WDT = 2, CSL_TMR_TIMMODE_DUAL_CHAINED = 3 }
 

This enum describes the mode of Timer (GPT/WDT/Chained/Unchained).

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enum  CSL_TmrState { CSL_TMR_TIMxxRS_RESET_ON = 0, CSL_TMR_TIMxxRS_RESET_OFF = 1 }
 

This enum describes the reset condition of Timer (ON/OFF).

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enum  CSL_TmrTstat { CSL_TMR_TSTAT_HIGH = 1, CSL_TMR_TSTAT_LOW = 0 }
 

This enum describes the status of Timer.

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enum  CSL_TmrWdflagBitStatus { CSL_TMR_WDFLAG_NOTIMEOUT = 0, CSL_TMR_WDFLAG_TIMEOUT = 1 }
 

This enumeration describes the flag bit status of the timer in watchdog mode.

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Enumeration Type Documentation

This enum describes the Timer Clock source selection.

Enumerator:
CSL_TMR_CLKSRC_INTERNAL 

timer clock INTERNAL source selection

CSL_TMR_CLKSRC_TMRINP 

timer clock Timer input pin source selection

This enum describes the mode of Timer Clock (Pulse/Clock).

Enumerator:
CSL_TMR_CP_PULSE 

Pulse mode

CSL_TMR_CP_CLOCK 

Clock mode

This enum describes the enabling/disabling of Timer.

Enumerator:
CSL_TMR_ENAMODE_DISABLE 

The timer is disabled and maintains current value

CSL_TMR_ENAMODE_ENABLE 

The timer is enabled one time

CSL_TMR_ENAMODE_CONT 

The timer is enabled continuously

This enum describes the commands used to control the GP timer through CSL_tmrHwControl().

General purpose global type def declarations

Enumerator:
CSL_TMR_CMD_LOAD_PRDLO 

Loads the GP Timer Period Register Low.

Parameters:
Uint32 *
CSL_TMR_CMD_LOAD_PRDHI 

Loads the GP Timer Period Register High.

Parameters:
Uint32 *
CSL_TMR_CMD_LOAD_PSCHI 

Loads the GP Timer Pre-scalar value for CNTHI.

Parameters:
Uint8 *
CSL_TMR_CMD_START_TIMLO 

Enable the GP timer Low.

Parameters:
CSL_TmrEnamode 
CSL_TMR_CMD_START_TIMHI 

Enable the GP timer High.

Parameters:
CSL_TmrEnamode 
CSL_TMR_CMD_STOP_TIMLO 

Stop the GP timer Low.

Parameters:
None 
CSL_TMR_CMD_STOP_TIMHI 

Stop the GP timer High.

Parameters:
None 
CSL_TMR_CMD_RESET_TIMLO 

Reset the GP timer Low.

Parameters:
None 
CSL_TMR_CMD_RESET_TIMHI 

Reset the GP timer High.

Parameters:
None 
CSL_TMR_CMD_START64 

Start the timer in GPtimer64 OR Chained mode.

Parameters:
None 
CSL_TMR_CMD_STOP64 

Stop the timer of GPtimer64 OR Chained.

Parameters:
CSL_TmrEnamode 
CSL_TMR_CMD_RESET64 

Reset the timer of GPtimer64 OR Chained.

Parameters:
None 
CSL_TMR_CMD_START_WDT 

Enable the timer in watchdog mode.

Parameters:
CSL_TmrEnamode 
CSL_TMR_CMD_LOAD_WDKEY 

Loads the watchdog key.

Parameters:
Uint16 

This enum describes the commands used to get status of various parameters of the GP timer. These values are used in CSL_tmrGetHwStatus().

Enumerator:
CSL_TMR_QUERY_COUNT_LO 

Gets the current value of the GP timer CNTLO register.

Parameters:
Uint32 *
CSL_TMR_QUERY_COUNT_HI 

Gets the current value of the GP timer CNTHI register.

Parameters:
Uint32 *
CSL_TMR_QUERY_TSTAT_LO 

This query command returns the status about whether the CNTLO is running or stopped.

Parameters:
CSL_TmrTstat 
CSL_TMR_QUERY_TSTAT_HI 

This query command returns the status about whether the CNTHI is running or stopped.

Parameters:
CSL_TmrTstat 
CSL_TMR_QUERY_WDFLAG_STATUS 

This query command returns the status about whether the timer is in watchdog mode or not.

Parameters:
CSL_WdflagBitStatus 

This enum describes the Timer input inverter control.

Enumerator:
CSL_TMR_INVINP_UNINVERTED 

Un inverted timer input drives timer

CSL_TMR_INVINP_INVERTED 

Inverted timer input drives timer

This enum describes the Timer output inverter control.

Enumerator:
CSL_TMR_INVOUTP_UNINVERTED 

Un inverted timer output

CSL_TMR_INVOUTP_INVERTED 

Inverted timer output

This enum describes whether the Timer Clock input is gated or not gated.

Enumerator:
CSL_TMR_CLOCK_INP_NOGATE 

timer input not gated

CSL_TMR_CLOCK_INP_GATE 

timer input gated

This enum describes the mode of Timer (GPT/WDT/Chained/Unchained).

Enumerator:
CSL_TMR_TIMMODE_GPT 

The timer is in 64-bit GP timer mode

CSL_TMR_TIMMODE_DUAL_UNCHAINED 

The timer is in dual 32-bit timer, unchained mode

CSL_TMR_TIMMODE_WDT 

The timer is in 64-bit Watchdog timer mode

CSL_TMR_TIMMODE_DUAL_CHAINED 

The timer is in dual 32-bit timer, chained mode

This enum describes the Timer Clock cycles (1/2/3/4).

Enumerator:
CSL_TMR_PWID_ONECLK 

One timer clock cycle

CSL_TMR_PWID_TWOCLKS 

Two timer clock cycle

CSL_TMR_PWID_THREECLKS 

Three timer clock cycle

CSL_TMR_PWID_FOURCLKS 

Four timer clock cycle

This enum describes the reset condition of Timer (ON/OFF).

Enumerator:
CSL_TMR_TIMxxRS_RESET_ON 

timer TIMxx is in reset

CSL_TMR_TIMxxRS_RESET_OFF 

timer CNTHI is not in reset. CNTHI can be used as a 32-bit timer

This enum describes the status of Timer.

Enumerator:
CSL_TMR_TSTAT_HIGH 

Timer status drives High

CSL_TMR_TSTAT_LOW 

Timer status drives Low

This enumeration describes the flag bit status of the timer in watchdog mode.

Enumerator:
CSL_TMR_WDFLAG_NOTIMEOUT 

No watchdog timeout occurred

CSL_TMR_WDFLAG_TIMEOUT 

Watchdog timeout occurred


Copyright 2012, Texas Instruments Incorporated