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Functions | |
CSL_IDEF_INLINE Uint32 | CSL_PLLC_getResetStatus (CSL_PllcHandle hPllc) |
CSL_IDEF_INLINE void | CSL_PLLC_setResetCtrlReg (CSL_PllcHandle hPllc, Uint16 key, Uint8 swRstEnable) |
CSL_IDEF_INLINE void | CSL_PLLC_getResetCtrlReg (CSL_PllcHandle hPllc, Uint16 *pKey, Uint8 *pSwRstEnable) |
CSL_IDEF_INLINE void | CSL_PLLC_setResetCfgReg (CSL_PllcHandle hPllc, Uint8 wdType, Uint8 resetType, Uint8 pllCtrlRstType) |
CSL_IDEF_INLINE void | CSL_PLLC_getResetCfgReg (CSL_PllcHandle hPllc, Uint8 *pWdType, Uint8 *pResetType, Uint8 *pPllCtrlRstType) |
CSL_IDEF_INLINE void | CSL_PLLC_setResetIsoReg (CSL_PllcHandle hPllc, Uint8 aif2Iso, Uint8 srIso, Uint8 srioIso) |
CSL_IDEF_INLINE void | CSL_PLLC_getResetIsoReg (CSL_PllcHandle hPllc, Uint8 *pAif2Iso, Uint8 *pSrIso, Uint8 *pSrioIso) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllCtrlPllEnSrc (CSL_PllcHandle hPllc, Uint8 value) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllCtrlPllEn (CSL_PllcHandle hPllc, Uint8 value) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllCtrlPllReset (CSL_PllcHandle hPllc, Uint8 value) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllCtrlPllPowerDown (CSL_PllcHandle hPllc, Uint8 value) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllCtrlReg (CSL_PllcHandle hPllc, Uint8 pllEn, Uint8 pllPwrDwn, Uint8 pllRst, Uint8 pllEnSrc) |
CSL_IDEF_INLINE void | CSL_PLLC_getPllCtrlReg (CSL_PllcHandle hPllc, Uint8 *pPllEn, Uint8 *pPllPwrDwn, Uint8 *pPllRst, Uint8 *pPllEnSrc) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllSecCtrlReg (CSL_PllcHandle hPllc, Uint8 pllSecCtrlVal) |
CSL_IDEF_INLINE Uint8 | CSL_PLLC_getPllSecCtrlReg (CSL_PllcHandle hPllc) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllMultiplierCtrlReg (CSL_PllcHandle hPllc, Uint8 pllmVal) |
CSL_IDEF_INLINE Uint8 | CSL_PLLC_getPllMultiplierCtrlReg (CSL_PllcHandle hPllc) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllPreDivReg (CSL_PllcHandle hPllc, Uint8 preDivEnable, Uint8 preDivRatio) |
CSL_IDEF_INLINE void | CSL_PLLC_getPllPreDivReg (CSL_PllcHandle hPllc, Uint8 *pPreDivEnable, Uint8 *pPreDivRatio) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllDivReg (CSL_PllcHandle hPllc, Uint8 divNum, Uint8 divEnable, Uint8 divRatio) |
CSL_IDEF_INLINE void | CSL_PLLC_getPllDivReg (CSL_PllcHandle hPllc, Uint8 divNum, Uint8 *pDivEnable, Uint8 *pDivRatio) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllPostDivReg (CSL_PllcHandle hPllc, Uint8 postDivEnable, Uint8 postDivRatio) |
CSL_IDEF_INLINE void | CSL_PLLC_getPllPostDivReg (CSL_PllcHandle hPllc, Uint8 *pPostDivEnable, Uint8 *pPostDivRatio) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllCmdReg (CSL_PllcHandle hPllc, Uint8 goSetEnable) |
CSL_IDEF_INLINE void | CSL_PLLC_getPllCmdReg (CSL_PllcHandle hPllc, Uint8 *pGoSetEnable) |
CSL_IDEF_INLINE void | CSL_PLLC_getPllStatusReg (CSL_PllcHandle hPllc, Uint8 *pGoStatus) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllAlignCtrlReg (CSL_PllcHandle hPllc, Uint32 alnCtlVal) |
CSL_IDEF_INLINE Uint32 | CSL_PLLC_getPllAlignCtrlReg (CSL_PllcHandle hPllc) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllDChangeReg (CSL_PllcHandle hPllc, Uint32 dChangeVal) |
CSL_IDEF_INLINE Uint32 | CSL_PLLC_getPllDChangeReg (CSL_PllcHandle hPllc) |
CSL_IDEF_INLINE void | CSL_PLLC_setPllClkEnableCtrlReg (CSL_PllcHandle hPllc, Uint32 auxClkEnable) |
CSL_IDEF_INLINE void | CSL_PLLC_getPllClkEnableCtrlReg (CSL_PllcHandle hPllc, Uint8 *pAuxClkEnable) |
CSL_IDEF_INLINE void | CSL_PLLC_getPllClkStatusReg (CSL_PllcHandle hPllc, Uint8 *pAuxOn) |
CSL_IDEF_INLINE Uint32 | CSL_PLLC_getPllSysClkStatusReg (CSL_PllcHandle hPllc) |
CSL_PllcHandle | CSL_PLLC_open (Int32 instNum) |
CSL_IDEF_INLINE Uint32 CSL_PLLC_getPllAlignCtrlReg | ( | CSL_PllcHandle | hPllc | ) |
============================================================================
CSL_PLLC_getPllAlignCtrlReg
Description
Retrieves the contents of PLL Clock Align control register.
Arguments
hPllc Handle to the PLLC instance
Return Value
Uint32
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_ALNCTL_ALN1_16
Example
CSL_PllcHandle hPllc; Uint32 alnCtlVal; ... alnCtlVal = CSL_PLLC_getPllAlignCtrlReg (hPllc);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getPllClkEnableCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pAuxClkEnable | |||
) |
============================================================================
CSL_PLLC_getPllClkEnableCtrlReg
Description
Retrieves the contents of PLL Clock Enable Control register.
Arguments
hPllc Handle to the PLLC instance pAuxClkEnable Indicates if AUXCLK is disabled/enabled
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_CKEN_AUXEN
Example
CSL_PllcHandle hPllc; Uint8 auxClkEnable; ... CSL_PLLC_getPllClkEnableCtrlReg (hPllc, &auxClkEnable);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getPllClkStatusReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pAuxOn | |||
) |
============================================================================
CSL_PLLC_getPllClkStatusReg
Description
Retrieves the contents of PLL Clock Status register.
Arguments
hPllc Handle to the PLLC instance pAuxOn Indicates if AUXCLK is ON
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_CKSTAT_AUXON
Example
CSL_PllcHandle hPllc; Uint8 auxOn; ... CSL_PLLC_getPllClkStatusReg (hPllc, &auxOn);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getPllCmdReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pGoSetEnable | |||
) |
============================================================================
CSL_PLLC_getPllCmdReg
Description
Retrieves the contents of PLL Command register.
Arguments
hPllc Handle to the PLLC instance pGoSetEnable GOSET bit status.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_PLLCMD_GOSET
Example
CSL_PllcHandle hPllc; Uint8 goSetEnable; ... CSL_PLLC_getPllCmdReg (hPllc, &goSetEnable);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getPllCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pPllEn, | |||
Uint8 * | pPllPwrDwn, | |||
Uint8 * | pPllRst, | |||
Uint8 * | pPllEnSrc | |||
) |
============================================================================
CSL_PLLC_getPllCtrlReg
Description
Retrieves the contents of PLL Control Register.
Arguments
hPllc Handle to the PLLC instance pPllEn PLL Enable bit. 0 indicates Bypass mode and 1 indicates PLL mode. pPllPwrDwn PLL Power-down mode select bit. 1 indicates PLLC is powered down and 0 indicates it is operational. pPllRst PLL Reset bit. 1 indicates reset is asserted and 0 indicates reset is cleared. pPllEnSrc PLL Enable Source bit. Indicates if PLLEN bit is enabled.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_PLLCTL_PLLEN, PLLC_PLLCTL_PLLPWRDN, PLLC_PLLCTL_PLLRST, PLLC_PLLCTL_PLLENSRC
Example
CSL_PllcHandle hPllc; Uint8 pllen, pllPwrDwn, pllRst, pllSrcEn; ... CSL_PLLC_getPllCtrlReg (hPllc, &pllen, &pllPwrDwn, &pllRst, &pllSrcEn);
============================================================================
CSL_IDEF_INLINE Uint32 CSL_PLLC_getPllDChangeReg | ( | CSL_PllcHandle | hPllc | ) |
============================================================================
CSL_PLLC_getPllDChangeReg
Description
Retrieves the contents of PLL Divider Ratio Change Status register.
Arguments
hPllc Handle to the PLLC instance
Return Value
Uint32
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_DCHANGE_SYS1_16
Example
CSL_PllcHandle hPllc; Uint32 dChangeVal; ... dChangeVal = CSL_PLLC_getPllDChangeReg (hPllc);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getPllDivReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | divNum, | |||
Uint8 * | pDivEnable, | |||
Uint8 * | pDivRatio | |||
) |
============================================================================
CSL_PLLC_getPllDivReg
Description
Returns the contents of PLL Divider Register corresponding to a given divider number.
Arguments
hPllc Handle to the PLLC instance divNum PLLC Divider register number. The divider number is 1 based. pDivEnable Indicates if divider is enabled pDivRatio Divider ratio bits
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_PLLDIV1_3_DNEN, PLLC_PLLDIV1_3_RATIO; PLLC_PLLDIV4_16_DNEN, PLLC_PLLDIV4_16_RATIO
Example
CSL_PllcHandle hPllc; Uint8 divEnable, divRatio; ... // Get div 3 settings CSL_PLLC_getPllDivReg (hPllc, 3, &divEnable, &divRatio);
============================================================================
CSL_IDEF_INLINE Uint8 CSL_PLLC_getPllMultiplierCtrlReg | ( | CSL_PllcHandle | hPllc | ) |
============================================================================
CSL_PLLC_getPllMultiplierCtrlReg
Description
Retrieves the contents of PLL Multiplier Control Register.
Arguments
hPllc Handle to the PLLC instance
Return Value
Uint8
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_PLLM_PLLM
Example
CSL_PllcHandle hPllc; Uint8 pllmVal; ... pllmVal = CSL_PLLC_getPllMultiplierCtrlReg (hPllc);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getPllPostDivReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pPostDivEnable, | |||
Uint8 * | pPostDivRatio | |||
) |
============================================================================
CSL_PLLC_getPllPostDivReg
Description
Returns the contents of PLL Post-Divider Register.
Arguments
hPllc Handle to the PLLC instance pPostDivEnable Indicates if post-divider is enabled pPostDivRatio Divider ratio bits
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_POSTDIV_RATIO, PLLC_POSTDIV_POSTDEN
Example
CSL_PllcHandle hPllc; Uint8 postDivEnable, postDivRatio; ... CSL_PLLC_getPllPostDivReg (hPllc, &postDivEnable, &postDivRatio);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getPllPreDivReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pPreDivEnable, | |||
Uint8 * | pPreDivRatio | |||
) |
============================================================================
CSL_PLLC_getPllPreDivReg
Description
Returns the contents of PLL Pre-Divider Register.
Arguments
hPllc Handle to the PLLC instance pPreDivEnable Indicates if pre-divider is enabled pPreDivRatio Divider ratio bits
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_PREDIV_RATIO, PLLC_PREDIV_PREDEN
Example
CSL_PllcHandle hPllc; Uint8 preDivEnable, preDivRatio; ... CSL_PLLC_getPllPreDivReg (hPllc, &preDivEnable, &preDivRatio);
============================================================================
CSL_IDEF_INLINE Uint8 CSL_PLLC_getPllSecCtrlReg | ( | CSL_PllcHandle | hPllc | ) |
============================================================================
CSL_PLLC_getPllSecCtrlReg
Description
Retrieves the contents of PLL Secondary Control Register.
Arguments
hPllc Handle to the PLLC instance
Return Value
Uint8
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_SECCTL_PLLSECCTL
Example
CSL_PllcHandle hPllc; Uint8 pllSecCtrlVal; ... pllSecCtrlVal = CSL_PLLC_getPllSecCtrlReg (hPllc);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getPllStatusReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pGoStatus | |||
) |
============================================================================
CSL_PLLC_getPllStatusReg
Description
Retrieves the contents of PLL Status register. Indicates the status of the GO operation.
Arguments
hPllc Handle to the PLLC instance pGoStatus GO operation status. 1 indicates GO operation is in progress. 0 indicates GO operation is not in progress.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_PLLSTAT_GOSTAT
Example
CSL_PllcHandle hPllc; Uint8 goStatus; ... CSL_PLLC_getPllStatusReg (hPllc, &goStatus);
============================================================================
CSL_IDEF_INLINE Uint32 CSL_PLLC_getPllSysClkStatusReg | ( | CSL_PllcHandle | hPllc | ) |
============================================================================
CSL_PLLC_getPllSysClkStatusReg
Description
Retrieves the contents of PLL SYSCLK Status register.
Arguments
hPllc Handle to the PLLC instance
Return Value
Uint32
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_SYSTAT_SYS1_16ON
Example
CSL_PllcHandle hPllc; Uint32 sysClkStatus; ... sysClkStatus = CSL_PLLC_getPllSysClkStatusReg (hPllc);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getResetCfgReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pWdType, | |||
Uint8 * | pResetType, | |||
Uint8 * | pPllCtrlRstType | |||
) |
============================================================================
CSL_PLLC_getResetCfgReg
Description
Retrieves the contents of Reset configuration register.
Arguments
hPllc Handle to the PLLC instance pWdType Reset type initiated by Watchdog timers. Returns 0 for hard reset and 1 for soft reset pResetType Reset type initiated by RESET. Returns 0 for hard reset and 1 for soft reset pPllCtrlRstType Reset type initiated by PLL controller. Returns 0 for hard reset and 1 for soft reset
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_RSTCFG_WDTYPEN, PLLC_RSTCFG_RESETTYPE, PLLC_RSTCFG_PLLCTLRSTTYPE
Example
CSL_PllcHandle hPllc; Uint8 wdType, resetType, pllCtrlRstType; ... CSL_PLLC_getResetCfgReg (hPllc, &wdType, &resetType, &pllCtrlRstType);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getResetCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint16 * | pKey, | |||
Uint8 * | pSwRstEnable | |||
) |
============================================================================
CSL_PLLC_getResetCtrlReg
Description
Retrieves the contents of the Reset control register
Arguments
hPllc Handle to the PLLC instance pKey Key value read pSwRstEnable Software reset enable bit read
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_RSTCTRL_KEY, PLLC_RSTCTRL_SWRST
Example
CSL_PllcHandle hPllc; Uint16 key; Uint8 swRstEnable ... CSL_PLLC_getResetCtrlReg (hPllc, &key, &swRstEnable);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_getResetIsoReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 * | pAif2Iso, | |||
Uint8 * | pSrIso, | |||
Uint8 * | pSrioIso | |||
) |
============================================================================
CSL_PLLC_getResetIsoReg
Description
Retrieves the contents of Reset Islolation register. Indicates the module clocks that are setup to work without pausing through non Power-on reset.
Arguments
hPllc Handle to the PLLC instance pAif2Iso Indicates if AIF2 module is reset isolated pSrIso Indicates if Smart Reflex module is reset isolated pSrioIso Indicates if SRIO module is reset isolated
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
PLLC_RSISO_AIF2ISO, PLLC_RSISO_SRISO, PLLC_RSISO_SRIOISO
Example
CSL_PllcHandle hPllc; Uint8 aif2Iso, srIso, srioIso; ... CSL_PLLC_getResetIsoReg (hPllc, &aif2Iso, &srIso, &srioIso);
============================================================================
CSL_IDEF_INLINE Uint32 CSL_PLLC_getResetStatus | ( | CSL_PllcHandle | hPllc | ) |
============================================================================
CSL_PLLC_getResetStatus
Description
Gets the Reset Type Status of the PLLC.
Arguments
hPllc Handle to the PLLC instance
Return Value
Uint32
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Reads
RSTYPE
Example
CSL_PllcHandle hPllc; Uint32 response; ... response = CSL_pllcGetResetStatus (hPllc);
============================================================================
CSL_PllcHandle CSL_PLLC_open | ( | Int32 | instNum | ) |
============================================================================
CSL_PLLC_open
Description
This API opens the PLLC instance. This should always be the first call to the CSL PLLC Functional layer. The handle which is returned from this call should be passed in all subsequent CSL APIs.
Return Value
CSL_PllcHandle - Handle to the PLLC Module
0 - Error.
Pre Condition
None
Post Condition
None
Affects
None
Example
CSL_PllcHandle hnd; ... hnd = CSL_PLLC_open (0); // Opens PLLC Instance 0 ...
===========================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllAlignCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint32 | alnCtlVal | |||
) |
============================================================================
CSL_PLLC_setPllAlignCtrlReg
Description
Sets up the contents of PLL Clock Align control register.
Arguments
hPllc Handle to the PLLC instance alnCtlVal Value to write to register.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_ALNCTL_ALN1_16
Example
CSL_PllcHandle hPllc; ... CSL_PLLC_setPllAlignCtrlReg (hPllc, 0);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllClkEnableCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint32 | auxClkEnable | |||
) |
============================================================================
CSL_PLLC_setPllClkEnableCtrlReg
Description
Sets up the contents of PLL Clock Enable Control register.
Arguments
hPllc Handle to the PLLC instance auxClkEnable Enable/disable PLLC output clock, AUXCLK
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_CKEN_AUXEN
Example
CSL_PllcHandle hPllc; ... CSL_PLLC_setPllClkEnableCtrlReg (hPllc, 0);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllCmdReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | goSetEnable | |||
) |
============================================================================
CSL_PLLC_setPllCmdReg
Description
Sets up the contents of PLL Command register. Can be used to enable the GOSET bit in PLLC Command register to initiate the GO operation or to clear it.
Arguments
hPllc Handle to the PLLC instance goSetEnable Set to 1 to enable GOSET bit and start GO operation and 0 to clear the bit.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_PLLCMD_GOSET
Example
CSL_PllcHandle hPllc; ... // Enable GO operation CSL_PLLC_setPllCmdReg (hPllc, 1);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllCtrlPllEn | ( | CSL_PllcHandle | hPllc, | |
Uint8 | value | |||
) |
============================================================================
CSL_PLLC_setPllCtrlPllEn
Description
Sets the PLLEN bit of PLL Control Register. This bit must be set to 0 to put PLLC in Bypass mode and to 1 to put it in PLL operational mode.
Arguments
hPllc Handle to the PLLC instance value 0/1 value to configure in PLL Enable bit. Set to 0 to put PLLC in Bypass mode and to 1 to put in PLL mode.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API. Enable configuration of PLLEN bit first using CSL_PLLC_setPllCtrlPllEnSrc () API by passing it a value 0.
Post Condition
None
Writes
PLLC_PLLCTL_PLLEN
Example
CSL_PllcHandle hPllc; ... // Enable PLLEN bit configuration CSL_PLLC_setPllCtrlPllEnSrc (hPllc, 0); // Put PLLC in Bypass mode CSL_PLLC_setPllCtrlPllEn (hPllc, 0); // Configure PLLM/Pre-Divider ... // Put PLLC back in PLL mode CSL_PLLC_setPllCtrlPllEn (hPllc, 1);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllCtrlPllEnSrc | ( | CSL_PllcHandle | hPllc, | |
Uint8 | value | |||
) |
============================================================================
CSL_PLLC_setPllCtrlPllEnSrc
Description
Sets up the PLLENSRC bit of PLL Control Register. Can be used to enable/disable configuration of PLLEN bit of PLLCTL register. Writes to PLLEN bit take effect on PLLC only when PLLENSRC bit is set to 0.
Arguments
hPllc Handle to the PLLC instance value 0/1 value to configure in PLLENSRC bit
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_PLLCTL_PLLENSRC
Example
CSL_PllcHandle hPllc; ... // Enable PLLEN bit configuration CSL_PLLC_setPllCtrlPllEnSrc (hPllc, 0);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllCtrlPllPowerDown | ( | CSL_PllcHandle | hPllc, | |
Uint8 | value | |||
) |
============================================================================
CSL_PLLC_setPllCtrlPllPowerDown
Description
Sets up the PLLPWRDWN bit of PLL Control Register. Must be set to 1 to power down PLL and to 0 to wake up the PLL.
Arguments
hPllc Handle to the PLLC instance value Value to configure in PLL Power-down mode select bit. Set to 1 to place PLLC in power-down mode and to 0 to wake it up.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API. PLLC must be put in Bypass mode by passing a value 0 to CSL_PLLC_setPllCtrlPllEn () API before powering up/down using this API.
Post Condition
None
Writes
PLLC_PLLCTL_PLLPWRDN
Example
CSL_PllcHandle hPllc; ... // Enable PLLEN bit configuration CSL_PLLC_setPllCtrlPllEnSrc (hPllc, 0); // Put PLLC in Bypass mode CSL_PLLC_setPllCtrlPllEn (hPllc, 0); // Power down PLL CSL_PLLC_setPllCtrlPllPowerDown (hPllc, 1); ... // Wake up PLL CSL_PLLC_setPllCtrlPllPowerDown (hPllc, 0); // Put PLLC back in PLL mode CSL_PLLC_setPllCtrlPllEn (hPllc, 1);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllCtrlPllReset | ( | CSL_PllcHandle | hPllc, | |
Uint8 | value | |||
) |
============================================================================
CSL_PLLC_setPllCtrlPllReset
Description
Sets up the PLLRST bit of PLL Control Register. Must be set to 1 to put PLLC in reset mode and to 0 to bring it out of reset.
Arguments
hPllc Handle to the PLLC instance value Value to configure in PLL Reset bit. Set to 1 to assert reset and 0 to release it from reset.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API. PLLC must be put in Bypass mode by passing a value 0 to CSL_PLLC_setPllCtrlPllEn () API before asserting/de-asserting reset using this API.
Post Condition
None
Writes
PLLC_PLLCTL_PLLRST
Example
CSL_PllcHandle hPllc; ... // Enable PLLEN bit configuration CSL_PLLC_setPllCtrlPllEnSrc (hPllc, 0); // Put PLLC in Bypass mode CSL_PLLC_setPllCtrlPllEn (hPllc, 0); // Put PLLC in reset CSL_PLLC_setPllCtrlPllReset (hPllc, 1); // Do PLLC configuration ... // Bring PLLC out of reset CSL_PLLC_setPllCtrlPllReset (hPllc, 0); // Put PLLC back in PLL mode CSL_PLLC_setPllCtrlPllEn (hPllc, 1);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | pllEn, | |||
Uint8 | pllPwrDwn, | |||
Uint8 | pllRst, | |||
Uint8 | pllEnSrc | |||
) |
============================================================================
CSL_PLLC_setPllCtrlReg
Description
Sets up the contents of PLL Control Register.
Arguments
hPllc Handle to the PLLC instance pllEn PLL Enable bit. Set to 0 to put PLLC in Bypass mode and to 1 to put in PLL mode. pllPwrDwn PLL Power-down mode select bit. Set to 1 to place PLLC in power-down mode. pllRst PLL Reset bit. Set to 1 to assert reset and 0 to release it from reset. pllEnSrc PLL Enable Source bit. Set to 1 to enable writes to PLLEN bit.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_PLLCTL_PLLEN, PLLC_PLLCTL_PLLPWRDN, PLLC_PLLCTL_PLLRST, PLLC_PLLCTL_PLLENSRC
Example
CSL_PllcHandle hPllc; ... CSL_PLLC_setPllCtrlReg (hPllc, 0, 0, 1, 1);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllDChangeReg | ( | CSL_PllcHandle | hPllc, | |
Uint32 | dChangeVal | |||
) |
============================================================================
CSL_PLLC_setPllDChangeReg
Description
Sets up the contents of PLL Divider Ratio Change Status register.
Arguments
hPllc Handle to the PLLC instance dChangeVal Value to write to register.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_DCHANGE_SYS1_16
Example
CSL_PllcHandle hPllc; ... CSL_PLLC_setPllDChangeReg (hPllc, 0);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllDivReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | divNum, | |||
Uint8 | divEnable, | |||
Uint8 | divRatio | |||
) |
============================================================================
CSL_PLLC_setPllDivReg
Description
Sets up the contents of any given PLL Divider Register corresponding to the divider number specified.
Arguments
hPllc Handle to the PLLC instance divNum PLLC Divider register number. The divider number is 1 based. divEnable Enable/disable the divider divRatio Divider ratio bits
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API. Ensure CSL_PLLC_getPllStatusReg () returns 0 for GOSTAT bit status before configuring the Dividers.
Post Condition
None
Writes
PLLC_PLLDIV1_3_DNEN, PLLC_PLLDIV1_3_RATIO; PLLC_PLLDIV4_16_DNEN, PLLC_PLLDIV4_16_RATIO
Example
CSL_PllcHandle hPllc; Uint8 goStatus; // Ensure no GO operation in progress already CSL_PLLC_getPllStatusReg (hPllc, &goStatus); while (goStatus != 0) { // wait some time and recheck GOSTAT status ... CSL_PLLC_getPllStatusReg (hPllc, &goStatus); } // Setup /1 divider rate and enable divider 1 CSL_PLLC_setPllDivReg (hPllc, 1, 0); // Set the respective ALNn bit in ALNCTL register CSL_PLLC_setPllAlignCtrlReg (hPllc, 1); // Start GO operation CSL_PLLC_setPllCmdReg (hPllc, 1); // Ensure GO operation completes CSL_PLLC_getPllStatusReg (hPllc, &goStatus); while (goStatus != 0) { // wait some time and recheck GOSTAT status ... CSL_PLLC_getPllStatusReg (hPllc, &goStatus); }
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllMultiplierCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | pllmVal | |||
) |
============================================================================
CSL_PLLC_setPllMultiplierCtrlReg
Description
Sets up the contents of PLL Multiplier Control Register.
Arguments
hPllc Handle to the PLLC instance pllmVal multiplier value to configure.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API. PLLC must be put in Bypass mode by passing a value 0 to CSL_PLLC_setPllCtrlPllEn () API before setting up the multiplier using this API.
Post Condition
None
Writes
PLLC_PLLM_PLLM
Example
CSL_PllcHandle hPllc; // Enable PLLEN bit configuration CSL_PLLC_setPllCtrlPllEnSrc (hPllc, 0); // Put PLLC in Bypass mode CSL_PLLC_setPllCtrlPllEn (hPllc, 0); // Configure PLLM/Pre-Divider // Setup x1 multiplier rate CSL_PLLC_setPllMultiplierCtrlReg (hPllc, 0); ... // Put PLLC back in PLL mode CSL_PLLC_setPllCtrlPllEn (hPllc, 1);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllPostDivReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | postDivEnable, | |||
Uint8 | postDivRatio | |||
) |
============================================================================
CSL_PLLC_setPllPostDivReg
Description
Sets up the contents of PLL Post-Divider Register.
Arguments
hPllc Handle to the PLLC instance postDivEnable Enable/disable the post-divider postDivRatio Divider ratio bits
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_POSTDIV_RATIO, PLLC_POSTDIV_POSTDEN
Example
CSL_PllcHandle hPllc; ... // Setup /1 divider rate and enable post divider CSL_PLLC_setPllPostDivReg (hPllc, 1, 0);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllPreDivReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | preDivEnable, | |||
Uint8 | preDivRatio | |||
) |
============================================================================
CSL_PLLC_setPllPreDivReg
Description
Sets up the contents of PLL Pre-Divider Register.
Arguments
hPllc Handle to the PLLC instance preDivEnable Enable/disable the pre-divider preDivRatio Divider ratio bits
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API. PLLC must be put in Bypass mode by passing a value 0 to CSL_PLLC_setPllCtrlPllEn () API before setting up the pre-divider using this API.
Post Condition
None
Writes
PLLC_PREDIV_RATIO, PLLC_PREDIV_PREDEN
Example
CSL_PllcHandle hPllc; // Enable PLLEN bit configuration CSL_PLLC_setPllCtrlPllEnSrc (hPllc, 0); // Put PLLC in Bypass mode CSL_PLLC_setPllCtrlPllEn (hPllc, 0); // Configure Pre-Divider // Setup /1 divider rate and enable divider CSL_PLLC_setPllPreDivReg (hPllc, 1, 0); ... // Put PLLC back in PLL mode CSL_PLLC_setPllCtrlPllEn (hPllc, 1);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setPllSecCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | pllSecCtrlVal | |||
) |
============================================================================
CSL_PLLC_setPllSecCtrlReg
Description
Sets up the contents of PLL Secondary Control Register.
Arguments
hPllc Handle to the PLLC instance pllSecCtrlVal Value to configure in the PLL Secondary control register.
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_SECCTL_PLLSECCTL
Example
CSL_PllcHandle hPllc; ... CSL_PLLC_setPllSecCtrlReg (hPllc, 0x10);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setResetCfgReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | wdType, | |||
Uint8 | resetType, | |||
Uint8 | pllCtrlRstType | |||
) |
============================================================================
CSL_PLLC_setResetCfgReg
Description
Sets up the contents of Reset configuration register.
Arguments
hPllc Handle to the PLLC instance wdType Reset type initiated by Watchdog timers. Set 0 for hard reset and 1 for soft reset resetType Reset type initiated by RESET. Set 0 for hard reset and 1 for soft reset pllCtrlRstType Reset type initiated by PLL controller. Set 0 for hard reset and 1 for soft reset
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API. Setup a valid key using CSL_PLLC_setResetCtrlReg () API.
Post Condition
None
Writes
PLLC_RSTCFG_WDTYPEN, PLLC_RSTCFG_RESETTYPE, PLLC_RSTCFG_PLLCTLRSTTYPE
Example
CSL_PllcHandle hPllc; ... CSL_PLLC_setResetCfgReg (hPllc, 0, 0, 0);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setResetCtrlReg | ( | CSL_PllcHandle | hPllc, | |
Uint16 | key, | |||
Uint8 | swRstEnable | |||
) |
============================================================================
CSL_PLLC_setResetCtrlReg
Description
Sets up the Key and Software Reset bit in Reset control register contents.
Arguments
hPllc Handle to the PLLC instance key Key value to setup swRstEnable Enable/disable software reset
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_RSTCTRL_KEY, PLLC_RSTCTRL_SWRST
Example
CSL_PllcHandle hPllc; ... CSL_PLLC_setResetCtrlReg (hPllc, CSL_PLLC_RSTCTRL_VALID_KEY, 1);
============================================================================
CSL_IDEF_INLINE void CSL_PLLC_setResetIsoReg | ( | CSL_PllcHandle | hPllc, | |
Uint8 | aif2Iso, | |||
Uint8 | srIso, | |||
Uint8 | srioIso | |||
) |
============================================================================
CSL_PLLC_setResetIsoReg
Description
Sets up the contents of Reset Islolation register. Can be used to setup the module clocks that need to be work without pausing through non Power-on reset.
Arguments
hPllc Handle to the PLLC instance aif2Iso Isolate AIF2 module? Set to 1 to isolate it srIso Isolate Smart Reflex module? Set to 1 to isolate it srioIso Isolate SRIO module? Set to 1 to isolate it
Return Value
void
Pre Condition
Must call CSL_PLLC_open () before calling any PLLC CSL API.
Post Condition
None
Writes
PLLC_RSISO_AIF2ISO, PLLC_RSISO_SRISO, PLLC_RSISO_SRIOISO
Example
CSL_PllcHandle hPllc; ... CSL_PLLC_setResetIsoReg (hPllc, 0, 0, 0);
============================================================================