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| #define CSL_EDMA3_ADDRMODE_CONST 1 |
Address Mode is such it wraps around after reaching FIFO width
| #define CSL_EDMA3_ADDRMODE_INCR 0 |
Address Mode is incremental
| #define CSL_EDMA3_BIDX_MAKE | ( | src, | |||
| dst | ) |
(Uint32)(\
CSL_FMKR(31, 16, (Uint32)dst) \
|CSL_FMKR(15, 0 , (Uint32)src)\
)
Used for creating the B index entry in the parameter ram
| #define CSL_EDMA3_CIDX_MAKE | ( | src, | |||
| dst | ) |
(Uint32)(\
CSL_FMKR(31, 16, (Uint32)dst) \
|CSL_FMKR(15, 0, (Uint32)src)\
)
Used for creating the C index entry in the parameter ram
| #define CSL_EDMA3_CNT_MAKE | ( | aCnt, | |||
| bCnt | ) |
(Uint32)(\
CSL_FMKR(15, 0, aCnt) \
|CSL_FMKR(31, 16, bCnt) \
)
Used for creating the A,B Count entry in the parameter ram
| #define CSL_EDMA3_FIFOWIDTH_128BIT 4 |
128 bit FIFO Width
| #define CSL_EDMA3_FIFOWIDTH_16BIT 1 |
16 bit FIFO Width
| #define CSL_EDMA3_FIFOWIDTH_256BIT 5 |
256 bit FIFO Width
| #define CSL_EDMA3_FIFOWIDTH_32BIT 2 |
32 bit FIFO Width
| #define CSL_EDMA3_FIFOWIDTH_64BIT 3 |
64 bit FIFO Width
| #define CSL_EDMA3_FIFOWIDTH_8BIT 0 |
8 bit FIFO Width
| #define CSL_EDMA3_FIFOWIDTH_NONE 0 |
Only for ease
| #define CSL_EDMA3_ITCCH_DIS 0 |
Intermediate transfer completion chaining disable
| #define CSL_EDMA3_ITCCH_EN 1 |
Intermediate transfer completion chaining enable
| #define CSL_EDMA3_ITCINT_DIS 0 |
Intermediate transfer completion interrupt disable
| #define CSL_EDMA3_ITCINT_EN 1 |
Intermediate transfer completion interrupt enable
| #define CSL_EDMA3_LINK_DEFAULT 0xFFFF |
Link to a Null Param set
| #define CSL_EDMA3_LINK_NULL 0xFFFF |
Link to a Null Param set
| #define CSL_EDMA3_LINKBCNTRLD_MAKE | ( | link, | |||
| bCntRld | ) |
(Uint32)(\
CSL_FMKR(15, 0 , (Uint32)link) \
|CSL_FMKR(31, 16, bCntRld)\
)
Used for creating the link and B count reload entry in the parameter ram
| #define CSL_EDMA3_MEMACCESS_AID0 0x0400 |
Allowed ID '0'
| #define CSL_EDMA3_MEMACCESS_AID1 0x0800 |
Allowed ID '1'
| #define CSL_EDMA3_MEMACCESS_AID2 0x1000 |
Allowed ID '2'
| #define CSL_EDMA3_MEMACCESS_AID3 0x2000 |
Allowed ID '3'
| #define CSL_EDMA3_MEMACCESS_AID4 0x4000 |
Allowed ID '4'
| #define CSL_EDMA3_MEMACCESS_AID5 0x8000 |
Allowed ID '5'
| #define CSL_EDMA3_MEMACCESS_EXT 0x0200 |
External Allowed ID. Requests with PrivID >= '6' are permitted if access type is allowed
| #define CSL_EDMA3_MEMACCESS_SR 0x0020 |
Supervisor Read permission
| #define CSL_EDMA3_MEMACCESS_SW 0x0010 |
Supervisor Write permission
| #define CSL_EDMA3_MEMACCESS_SX 0x0008 |
Supervisor Execute permission
| #define CSL_EDMA3_MEMACCESS_UR 0x0004 |
User Read permission
| #define CSL_EDMA3_MEMACCESS_UW 0x0002 |
User Write permission
| #define CSL_EDMA3_MEMACCESS_UX 0x0001 |
User Execute permission
| #define CSL_EDMA3_OPT_MAKE | ( | itcchEn, | |||
| tcchEn, | |||||
| itcintEn, | |||||
| tcintEn, | |||||
| tcc, | |||||
| tccMode, | |||||
| fwid, | |||||
| stat, | |||||
| syncDim, | |||||
| dam, | |||||
| sam | ) |
(Uint32)(\
CSL_FMKR(23,23,itcchEn) \
|CSL_FMKR(22,22,tcchEn) \
|CSL_FMKR(21,21,itcintEn) \
|CSL_FMKR(20,20,tcintEn) \
|CSL_FMKR(17,12,tcc) \
|CSL_FMKR(11,11,tccMode) \
|CSL_FMKR(10,8,fwid) \
|CSL_FMKR(3,3,stat) \
|CSL_FMKR(2,2,syncDim) \
|CSL_FMKR(1,1,dam) \
|CSL_FMKR(0,0,sam))
Used for creating the options entry in the parameter ram
| #define CSL_EDMA3_REGION_GLOBAL -1 |
EDMA Regions: Global and 8 SHADOW Regions.
| #define CSL_EDMA3_STATIC_DIS 0 |
Disable Static
| #define CSL_EDMA3_STATIC_EN 1 |
Enable Static
| #define CSL_EDMA3_SYNC_A 0 |
A synchronized transfer
| #define CSL_EDMA3_SYNC_AB 1 |
AB synchronized transfer
| #define CSL_EDMA3_TCC_EARLY 1 |
Early Completion
| #define CSL_EDMA3_TCC_NORMAL 0 |
Normal Completion
| #define CSL_EDMA3_TCCH_DIS 0 |
Transfer completion chaining disable
| #define CSL_EDMA3_TCCH_EN 1 |
Transfer completion chaining enable
| #define CSL_EDMA3_TCINT_DIS 0 |
Transfer completion interrupt disable
| #define CSL_EDMA3_TCINT_EN 1 |
Transfer completion interrupt enable
| #define CSL_EDMA3_TRIGWORD_A_B_CNT 2 |
Trigger word AB count
| #define CSL_EDMA3_TRIGWORD_CCNT 7 |
Trigger word C count
| #define CSL_EDMA3_TRIGWORD_DEFAULT 7 |
Last trigger word in a QDMA parameter set
| #define CSL_EDMA3_TRIGWORD_DST 3 |
Trigger word destination
| #define CSL_EDMA3_TRIGWORD_LINK_BCNTRLD 5 |
Trigger word B count reload
| #define CSL_EDMA3_TRIGWORD_OPT 0 |
Trigger word option field
| #define CSL_EDMA3_TRIGWORD_SRC 1 |
Trigger word source
| #define CSL_EDMA3_TRIGWORD_SRC_DST_BIDX 4 |
Trigger word src and dst B index
| #define CSL_EDMA3_TRIGWORD_SRC_DST_CIDX 6 |
Trigger word src and dst C index