# CACHE Functions
[CACHE]

## Functions
CSL_IDEF_INLINE void | CACHE_enableCaching (Uint8 mar)
CSL_IDEF_INLINE void | CACHE_disableCaching (Uint8 mar)
CSL_IDEF_INLINE void | CACHE_getMemRegionInfo (Uint8 mar, Uint8 *pcx, Uint8 *pfx)
CSL_IDEF_INLINE void | CACHE_setMemRegionInfo (Uint8 mar, Uint8 pcx, Uint8 pfx)
CSL_IDEF_INLINE void | CACHE_setL1DSize (CACHE_L1Size newSize)
CSL_IDEF_INLINE CACHE_L1Size | CACHE_getL1DSize (void)
CSL_IDEF_INLINE void | CACHE_freezeL1D (void)
CSL_IDEF_INLINE void | CACHE_unfreezeL1D (void)
CSL_IDEF_INLINE Uint32 | CACHE_getPrevL1DMode (void)
CSL_IDEF_INLINE void | CACHE_invAllL1dWait (void)
CSL_IDEF_INLINE void | CACHE_invAllL1d (CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_wbAllL1dWait (void)
CSL_IDEF_INLINE void | CACHE_wbAllL1d (CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_wbInvAllL1dWait (void)
CSL_IDEF_INLINE void | CACHE_wbInvAllL1d (CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_invL1dWait (void)
CSL_IDEF_INLINE void | CACHE_invL1d (void *blockPtr, Uint32 byteCnt, CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_wbL1dWait (void)
CSL_IDEF_INLINE void | CACHE_wbL1d (void *blockPtr, Uint32 byteCnt, CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_wbInvL1dWait (void)
CSL_IDEF_INLINE void | CACHE_wbInvL1d (void *blockPtr, Uint32 byteCnt, CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_setL1PSize (CACHE_L1Size newSize)
CSL_IDEF_INLINE CACHE_L1Size | CACHE_getL1PSize (void)
CSL_IDEF_INLINE void | CACHE_freezeL1P (void)
CSL_IDEF_INLINE void | CACHE_unfreezeL1P (void)
CSL_IDEF_INLINE Uint32 | CACHE_getPrevL1PMode (void)
CSL_IDEF_INLINE void | CACHE_invL1pWait (void)
CSL_IDEF_INLINE void | CACHE_invL1p (void *blockPtr, Uint32 byteCnt, CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_invAllL1pWait (void)
CSL_IDEF_INLINE void | CACHE_invAllL1p (CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_setL2Size (CACHE_L2Size newSize)
CSL_IDEF_INLINE CACHE_L2Size | CACHE_getL2Size (void)
CSL_IDEF_INLINE void | CACHE_freezeL2 (void)
CSL_IDEF_INLINE void | CACHE_unfreezeL2 (void)
CSL_IDEF_INLINE void | CACHE_wbL2Wait (void)
CSL_IDEF_INLINE void | CACHE_wbL2 (void *blockPtr, Uint32 byteCnt, CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_invL2Wait (void)
CSL_IDEF_INLINE void | CACHE_invL2 (void *blockPtr, Uint32 byteCnt, CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_wbInvL2Wait (void)
CSL_IDEF_INLINE void | CACHE_wbInvL2 (void *blockPtr, Uint32 byteCnt, CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_wbAllL2Wait (void)
CSL_IDEF_INLINE void | CACHE_wbAllL2 (CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_invAllL2Wait (void)
CSL_IDEF_INLINE void | CACHE_invAllL2 (CACHE_Wait wait)
CSL_IDEF_INLINE void | CACHE_wbInvAllL2Wait (void)
CSL_IDEF_INLINE void | CACHE_wbInvAllL2 (CACHE_Wait wait)

## Function Documentation

CSL_IDEF_INLINE void CACHE_disableCaching | ( | Uint8 | mar | ) |

============================================================================
CACHE_disableCaching

Description
This function disables caching for a specific memory region.

Arguments

              mar      Memory region for which cache is to be disabled.

Return Value
None

Pre Condition
None

Post Condition
Memory region is now *not* cacheable.

Writes
CGEM_MAR0_PC=0

Example

            CACHE_disableCaching (20);

=============================================================================

CSL_IDEF_INLINE void CACHE_enableCaching | ( | Uint8 | mar | ) |

============================================================================
CACHE_enableCaching

Description
This function enables caching for a specific memory region.

Arguments

              mar      Memory region for which cache is to be enabled.

Return Value
None

Pre Condition
None

Post Condition
Memory region is now cacheable.

Writes
CGEM_MAR0_PC=1

Example

            CACHE_enableCaching (20);

=============================================================================

CSL_IDEF_INLINE void CACHE_freezeL1D | ( | void |  | ) |

============================================================================
CACHE_freezeL1D

Description
This function is used to freeze the L1D cache.

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
None

Writes
CGEM_L1DCC_OPER=1

Example

            CACHE_freezeL1D();

=============================================================================

CSL_IDEF_INLINE void CACHE_freezeL1P | ( | void |  | ) |

============================================================================
CACHE_freezeL1P

Description
This function is used to freeze the L1P cache.

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
None

Writes
CGEM_L1PCC_OPER=1

Example

            CACHE_freezeL1P();

=============================================================================

CSL_IDEF_INLINE void CACHE_freezeL2 | ( | void |  | ) |

============================================================================
CACHE_freezeL2

Description
This function is used to freeze the L2 Cache

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
The L2 Cache is frozen.

Example

            CACHE_freezeL2();

=============================================================================

CSL_IDEF_INLINE CACHE_L1Size CACHE_getL1DSize | ( | void |  | ) |

============================================================================
CACHE_getL1DSize

Description
This function is used to get the L1 Data Cache Size.

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
None

Reads
CGEM_L1DCFG_L1DMODE

Example

            CACHE_L1Size cacheSize;

            cacheSize = CACHE_getL1DSize();

=============================================================================

CSL_IDEF_INLINE CACHE_L1Size CACHE_getL1PSize | ( | void |  | ) |

============================================================================
CACHE_getL1PSize

Description
This function is used to get the L1P Cache Size.

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
None

Reads
CGEM_L1PCFG_L1PMODE

Example

            CACHE_L1Size cacheSize;

            cacheSize = CACHE_getL1PSize();

=============================================================================

CSL_IDEF_INLINE CACHE_L2Size CACHE_getL2Size | ( | void |  | ) |

============================================================================
CACHE_getL2Size

Description
This function is used to get the L2 cache size.

Arguments
None

Return Value
CACHE_L2Size

Pre Condition
None

Post Condition
None

Reads
CGEM_L2CFG_L2MODE

Example

            CACHE_L2Size size;

            size = CACHE_getL2Size();

=============================================================================

CSL_IDEF_INLINE void CACHE_getMemRegionInfo | ( | Uint8 | mar,
|  | Uint8 * | pcx,
|  | Uint8 * | pfx |
| ) |  |  |

============================================================================
CACHE_getMemRegionInfo

Description
This function is used to get memory region information.

Arguments

              mar      Memory region for which the information is required.
              pcx      Is address cacheable in external cache (MSMC)
              pfx      Is address prefetchable

Return Value
None

Pre Condition
None

Post Condition
None

Reads
CGEM_MAR0_PCX, CGEM_MAR0_PFX

Example

            Uint8 pcx;
            Uint8 pfx;

            // Get the memory region information for 20
            CACHE_getMemRegionInfo (20, &pcx, &pfx);

=============================================================================

CSL_IDEF_INLINE Uint32 CACHE_getPrevL1DMode | ( | void |  | ) |

============================================================================
CACHE_getPrevL1DMode

Description
This function is used get the previous operating state of the L1D cache

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
None

Reads
CGEM_L1DCC_POPER

Example

            Uint32 prev;

            prev = CACHE_getPrevL1DMode();

=============================================================================

CSL_IDEF_INLINE Uint32 CACHE_getPrevL1PMode | ( | void |  | ) |

============================================================================
CACHE_getPrevL1PMode

Description
This function is used get the previous operating state of the L1P cache

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
None

Reads
CGEM_L1PCC_POPER

Example

            Uint32  prev;

            prev = CACHE_getPrevL1PMode();

=============================================================================

CSL_IDEF_INLINE void CACHE_invAllL1d | ( | CACHE_Wait | wait | ) |

============================================================================
CACHE_invAllL1d

Description
This function is used to globally invalidate the L1D cache.

Arguments

              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The L1D Cache is being invalidated.

Writes
CGEM_L1DINV_I=1

Example

            CACHE_invAllL1d(CACHE_WAIT); // Invalidate the L1D cache

=============================================================================

CSL_IDEF_INLINE void CACHE_invAllL1dWait | ( | void |  | ) |

============================================================================
CACHE_invAllL1dWait

Description
This function is used to wait for the L1D global invalidate operation to complete. This API should be used only if the CACHE_invAllL1d was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_invAllL1d(wait=CACHE_NOWAIT) must be called.

Post Condition
None

Reads
CGEM_L1DINV_I=0

Example

            CACHE_invAllL1d(CACHE_NOWAIT); // Invalidate the L1D cache
            ...
            CACHE_invAllL1dWait();        // Wait for the invalidate operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_invAllL1p | ( | CACHE_Wait | wait | ) |

============================================================================
CACHE_invAllL1p

Description
This function is used to invalidate the entire L1P Cache

Arguments

              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The entire L1P cache is being invalidated.

Writes
CGEM_L1PINV_I=1

Example

            CACHE_invAllL1p(CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_invAllL1pWait | ( | void |  | ) |

============================================================================
CACHE_invAllL1pWait

Description
This function is used to wait for the L1P invalidate operation to complete. This API should be used only if the CACHE_invAllL1p was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_invAllL1p(wait=CACHE_NOWAIT) must be called.

Post Condition
The L1P Cache is invalidated.

Reads
CGEM_L1PINV_I=0

Example

            CACHE_invAllL1p(CACHE_NOWAIT);
            ...
            CACHE_invAllL1pWait();        // Wait for the Invalidate operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_invAllL2 | ( | CACHE_Wait | wait | ) |

============================================================================
CACHE_invAllL2

Description
This function is used to invalidate all the contents of the L2 Cache.

Arguments

              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the L2 Cache are being invalidated.

Writes
CGEM_L2INV_I=1

Example

            // Invalidate the contents of the L2 Cache.
            CACHE_invAllL2(CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_invAllL2Wait | ( | void |  | ) |

============================================================================
CACHE_invAllL2Wait

Description
This function is used to wait for the L2 Invalidate operation to complete. This API should be used only if the CACHE_invAllL2 was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_invAllL2(wait=CACHE_NOWAIT) must be called.

Post Condition
The contents of the L2 Cache have been invalidated

Reads
CGEM_L2INV_I=0

Example

            // Invalidate the contents of the L2 Cache.
            CACHE_invAllL2(CACHE_NOWAIT);

            // Wait for the operation to complete.
            CACHE_invAllL2Wait();

=============================================================================

CSL_IDEF_INLINE void CACHE_invL1d | ( | void * | blockPtr,
|  | Uint32 | byteCnt,
|  | CACHE_Wait | wait |
| ) |  |  |

============================================================================
CACHE_invL1d

Description
This function is used to invalidate a block in the L1D Cache. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size.

Arguments

              blockPtr      Address of the block which is to be invalidated
              byteCnt       Size of the block to be invalidated.
              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the blockPtr are being invalidated

Writes
CGEM_L1DIBAR_ADDR,CGEM_L1DIWC_WC

Example

            Uint8* ptr_buffer;

            // Invalidate 128 bytes of the buffer.
            CACHE_invL1d((void *)ptr_buffer, 128, CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_invL1dWait | ( | void |  | ) |

============================================================================
CACHE_invL1dWait

Description
This function is used to wait for the L1D invalidate block operation to complete. This API should be used only if the CACHE_invL1d was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_invL1d(wait=CACHE_NOWAIT) must be called.

Post Condition
The L1D Block Cache is invalidated.

Reads
CGEM_L1DIWC_WC=0

Example

            CACHE_invL1d((void *)ptr_buffer, 128, CACHE_NOWAIT);
            ...
            CACHE_invL1dWait();        // Wait for the Invalidate/Writeback operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_invL1p | ( | void * | blockPtr,
|  | Uint32 | byteCnt,
|  | CACHE_Wait | wait |
| ) |  |  |

============================================================================
CACHE_invL1p

Description
This function is used to invalidate the L1P Cache pointed by the block address. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size.

Arguments

              blockPtr      Address of the block which is to be invalidated
              byteCnt       Size of the block to be invalidated.
              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the blockPtr are being invalidated

Writes
CGEM_L1PIBAR_ADDR,CGEM_L1PIWC_WC

Example

            // Invalidate the 128 bytes of the function 'foo'
            CACHE_invL1p((void *)&foo, 128, CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_invL1pWait | ( | void |  | ) |

============================================================================
CACHE_invL1pWait

Description
This function is used to wait for the L1D invalidate block operation to complete. This API should be used only if the CACHE_invL1p was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_invL1p(wait=CACHE_NOWAIT) must be called.

Post Condition
The L1D Block Cache is invalidated.

Reads
CGEM_L1PIWC_WC=0

Example

            CACHE_invL1p((void *)&foo, 128, CACHE_NOWAIT);
            ...
            CACHE_invL1pWait();        // Wait for the Invalidate operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_invL2 | ( | void * | blockPtr,
|  | Uint32 | byteCnt,
|  | CACHE_Wait | wait |
| ) |  |  |

============================================================================
CACHE_invL2

Description
This function is used to invalidate the contents of the L2 Cache. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size.

Arguments

              blockPtr      Address of the block which is to be invalidated
              byteCnt       Size of the block to be invalidated.
              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the L2 Cache are being invalidated.

Writes
CGEM_L2IBAR_ADDR,CGEM_L2IWC_WC

Example

            Uint8* ptr_buffer;

            // Invalidate the contents of the buffer.
            CACHE_invL2(ptr_buffer, 100, CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_invL2Wait | ( | void |  | ) |

============================================================================
CACHE_invL2Wait

Description
This function is used to wait for the L2 invalidate block operation to complete. This API should be used only if the CACHE_invL2 was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_invL2(wait=CACHE_NOWAIT) must be called.

Post Condition
Invalidate the contents of the L2 Cache.

Reads
CGEM_L2IWC_WC=0

Example

            CACHE_invL2((void *)ptr_buffer, 128, CACHE_NOWAIT);
            ...
            CACHE_invL2Wait();        // Wait for the Invalidate operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_setL1DSize | ( | CACHE_L1Size | newSize | ) |

============================================================================
CACHE_setL1DSize

Description
This function is used to set the L1 Data Cache Size.

Arguments

              newSize      Cache Size to be configured.

Return Value
None

Pre Condition
None

Post Condition
None

Writes
CGEM_L1DCFG_L1DMODE

Example

            CACHE_setL1DSize(1); // Configure 4K Cache Size

=============================================================================

CSL_IDEF_INLINE void CACHE_setL1PSize | ( | CACHE_L1Size | newSize | ) |

============================================================================
CACHE_setL1PSize

Description
This function is used to set the L1P Cache Size.

Arguments

              newSize      Cache Size to be configured.

Return Value
None

Pre Condition
None

Post Condition
None

Writes
CGEM_L1PCFG_L1PMODE

Example

            CACHE_setL1PSize(1); // Configure 4K Cache Size

=============================================================================

CSL_IDEF_INLINE void CACHE_setL2Size | ( | CACHE_L2Size | newSize | ) |

============================================================================
CACHE_setL2Size

Description
This function is used to set the new size of the L2 Cache.

Arguments

              newSize   New Size of the L2 Cache to be set.

Return Value
None

Pre Condition
None

Post Condition
The L2 Cache is configured to use the new size.

Writes
CGEM_L2CFG_L2MODE

Example

            CACHE_setL2Size(CACHE_32KCACHE); // Use 32K L2 Cache.

=============================================================================

CSL_IDEF_INLINE void CACHE_setMemRegionInfo | ( | Uint8 | mar,
|  | Uint8 | pcx,
|  | Uint8 | pfx |
| ) |  |  |

============================================================================
CACHE_setMemRegionInfo

Description
This function is used to set memory region information.

Arguments

              mar      Memory region for which the information is required.
              pcx      Is address cacheable in external cache (MSMC)
              pfx      Is address prefetchable

Return Value
None

Pre Condition
None

Post Condition
None

Writes
CGEM_MAR0_PCX, CGEM_MAR0_PFX

Example

            Uint8 pcx;
            Uint8 pfx;

            // Get the memory region information for 20
            CACHE_getMemRegionInfo (20, &pcx, &pfx);
            ...
            // Ensure Memory Region 20 is not prefetchable.
            CACHE_setMemRegionInfo(20, pcx, 0);

=============================================================================

CSL_IDEF_INLINE void CACHE_unfreezeL1D | ( | void |  | ) |

============================================================================
CACHE_unfreezeL1D

Description
This function is used to unfreeze the L1D cache.

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
None

Writes
CGEM_L1DCC_OPER=0

Example

            CACHE_unfreezeL1D();

=============================================================================

CSL_IDEF_INLINE void CACHE_unfreezeL1P | ( | void |  | ) |

============================================================================
CACHE_unfreezeL1P

Description
This function is used to unfreeze the L1D cache.

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
None

Writes
CGEM_L1PCC_OPER=0

Example

            CACHE_unfreezeL1D();

=============================================================================

CSL_IDEF_INLINE void CACHE_unfreezeL2 | ( | void |  | ) |

============================================================================
CACHE_unfreezeL2

Description
This function is used to unfreeze the L2 Cache

Arguments
None

Return Value
None

Pre Condition
None

Post Condition
The L2 Cache is unfrozen

Example

            CACHE_unfreezeL2();

=============================================================================

CSL_IDEF_INLINE void CACHE_wbAllL1d | ( | CACHE_Wait | wait | ) |

============================================================================
CACHE_wbAllL1d

Description
This function is used to writeback the dirty lines of the L1D Cache

Arguments

              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The dirty lines of the L1D Cache are being written back

Writes
CGEM_L1DWB_C=1

Example

            CACHE_wbAllL1d(CACHE_WAIT); // Writeback the Dirty Lines of the L1D cache

=============================================================================

CSL_IDEF_INLINE void CACHE_wbAllL1dWait | ( | void |  | ) |

============================================================================
CACHE_wbAllL1dWait

Description
This function is used to wait for the L1D writeback operation to complete. This API should be used only if the CACHE_wbAllL1d was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_wbAllL1d(wait=CACHE_NOWAIT) must be called.

Post Condition
The L1D Dirty lines are written back

Reads
CGEM_L1DWB_C=0

Example

            CACHE_wbAllL1d(CACHE_NOWAIT); // Writeback the L1D cache
            ...
            CACHE_wbAllL1dWait();        // Wait for the writeback operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_wbAllL2 | ( | CACHE_Wait | wait | ) |

============================================================================
CACHE_wbAllL2

Description
This function is used to write back all the contents of the L2 Cache.

Arguments

              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the L2 Cache are being written back.

Writes
CGEM_L2WB_C=1

Example

            // Writeback the contents of the L2 Cache.
            CACHE_wbAllL2(CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_wbAllL2Wait | ( | void |  | ) |

============================================================================
CACHE_wbAllL2Wait

Description
This function is used to wait for the L2 Writeback & invalidate operation to complete. This API should be used only if the CACHE_wbAllL2 was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_wbAllL2(wait=CACHE_NOWAIT) must be called.

Post Condition
The contents of the L2 Cache have been written back

Reads
CGEM_L2WB_C=0

Example

            // Writeback the contents of the L2 Cache.
            CACHE_wbAllL2(CACHE_NOWAIT);

            // Wait for the operation to complete.
            CACHE_wbAllL2Wait();

=============================================================================

CSL_IDEF_INLINE void CACHE_wbInvAllL1d | ( | CACHE_Wait | wait | ) |

============================================================================
CACHE_wbInvAllL1d

Description
This function is used to invalidate and writeback the dirty lines of the L1D Cache

Arguments

              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
Invalidates and Writebacks the dirty lines of the L1D Cache

Writes
CGEM_L1DWBINV_C=1

Example

            CACHE_wbInvAllL1d(CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_wbInvAllL1dWait | ( | void |  | ) |

============================================================================
CACHE_wbInvAllL1dWait

Description
This function is used to wait for the L1D writeback invalidate operation to complete. This API should be used only if the CACHE_wbInvAllL1d was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_wbInvAllL1d(wait=CACHE_NOWAIT) must be called.

Post Condition
The L1D Dirty lines are written back

Reads
CGEM_L1DWBINV_C=0

Example

            CACHE_wbInvAllL1d(CACHE_NOWAIT); // Invalidate/Writeback the L1D cache
            ...
            CACHE_wbInvAllL1dWait();        // Wait for the Invalidate/Writeback operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_wbInvAllL2 | ( | CACHE_Wait | wait | ) |

============================================================================
CACHE_wbInvAllL2

Description
This function is used to writeback and invalidate all the contents of the L2 Cache.

Arguments

              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the L2 Cache are being written back & invalidated.

Writes
CGEM_L2WBINV_C=1

Example

            // Invalidate the contents of the L2 Cache.
            CACHE_wbInvAllL2(CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_wbInvAllL2Wait | ( | void |  | ) |

============================================================================
CACHE_wbInvAllL2Wait

Description
This function is used to wait for the L2 Writeback and Invalidate operation to complete. This API should be used only if the CACHE_wbInvAllL2 was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_wbInvAllL2(wait=CACHE_NOWAIT) must be called.

Post Condition
The contents of the L2 Cache have been invalidated and written back

Reads
CGEM_L2WBINV_C=0

Example

            // Writeback & Invalidate the contents of the L2 Cache.
            CACHE_wbInvAllL2(CACHE_NOWAIT);

            // Wait for the operation to complete.
            CACHE_wbInvAllL2Wait();

=============================================================================

CSL_IDEF_INLINE void CACHE_wbInvL1d | ( | void * | blockPtr,
|  | Uint32 | byteCnt,
|  | CACHE_Wait | wait |
| ) |  |  |

============================================================================
CACHE_wbInvL1d

Description
This function is used to invalidate and writeback the dirty lines of the block address. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size.

Arguments

              blockPtr      Address of the block which is to be invalidated/written back
              byteCnt       Size of the block to be invalidated/written back.
              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the blockPtr are being invalidated and the dirty lines are written back

Writes
CGEM_L1DWIBAR_ADDR,CGEM_L1DWIWC_WC

Example

            Uint8* ptr_buffer;

            // Writeback/Invalidate 128 bytes of the buffer.
            CACHE_wbInvL1d((void *)ptr_buffer, 128, CACHE_WAIT);

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CSL_IDEF_INLINE void CACHE_wbInvL1dWait | ( | void |  | ) |

============================================================================
CACHE_wbInvL1dWait

Description
This function is used to wait for the L1D invalidate/writeback block operation to complete. This API should be used only if the CACHE_wbInvL1d was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_wbInvL1d(wait=CACHE_NOWAIT) must be called.

Post Condition
The dirty lines of the L1D Block Cache have been written back and the cache contents pointed to by the block address are also invalidated.

Reads
CGEM_L1DWIWC_WC=0

Example

            CACHE_wbInvL1d((void *)ptr_buffer, 128, CACHE_NOWAIT);
            ...
            CACHE_wbInvL1dWait();        // Wait for the operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_wbInvL2 | ( | void * | blockPtr,
|  | Uint32 | byteCnt,
|  | CACHE_Wait | wait |
| ) |  |  |

============================================================================
CACHE_wbInvL2

Description
This function is used to write back and invalidate the contents of the L2 Cache. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size.

Arguments

              blockPtr      Address of the block which is to be written back & invalidated
              byteCnt       Size of the block to be written back & invalidated.
              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the L2 Cache are being written back & invalidated.

Writes
CGEM_L2WIBAR_ADDR,CGEM_L2WIWC_WC

Example

            Uint8* ptr_buffer;

            // Invalidate the contents of the buffer.
            CACHE_wbInvL2(ptr_buffer, 100, CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_wbInvL2Wait | ( | void |  | ) |

============================================================================
CACHE_wbInvL2Wait

Description
This function is used to wait for the L2 Writeback & invalidate block operation to complete. This API should be used only if the CACHE_wbInvL2 was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_wbInvL2(wait=CACHE_NOWAIT) must be called.

Post Condition
Invalidate the contents of the L2 Cache.

Reads
CGEM_L2WIWC_WC=0

Example

            CACHE_wbInvL2((void *)ptr_buffer, 128, CACHE_NOWAIT);
            ...
            CACHE_wbInvL2Wait();  // Wait for the Writeback-Invalidate operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_wbL1d | ( | void * | blockPtr,
|  | Uint32 | byteCnt,
|  | CACHE_Wait | wait |
| ) |  |  |

============================================================================
CACHE_wbL1d

Description
This function is used to writeback the dirty lines of the block address. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size.

Arguments

              blockPtr      Address of the block which is to be written back
              byteCnt       Size of the block to be written back.
              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The contents of the blockPtr are being written back

Writes
CGEM_L1DWBAR_ADDR,CGEM_L1DWWC_WC

Example

            Uint8* ptr_buffer;

            // Writeback 128 bytes of the buffer.
            CACHE_wbL1d((void *)ptr_buffer, 128, CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_wbL1dWait | ( | void |  | ) |

============================================================================
CACHE_wbL1dWait

Description
This function is used to wait for the L1D writeback block operation to complete. This API should be used only if the CACHE_wbL1d was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_wbL1d(wait=CACHE_NOWAIT) must be called.

Post Condition
The dirty lines of the L1D Block Cache have been written back.

Reads
CGEM_L1DWWC_WC=0

Example

            CACHE_wbL1d((void *)ptr_buffer, 128, CACHE_NOWAIT);
            ...
            CACHE_wbL1dWait();        // Wait for the writeback operation to complete.

=============================================================================

CSL_IDEF_INLINE void CACHE_wbL2 | ( | void * | blockPtr,
|  | Uint32 | byteCnt,
|  | CACHE_Wait | wait |
| ) |  |  |

============================================================================
CACHE_wbL2

Description
This function is used to writeback the contents of the L2 Cache. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size.

Arguments

              blockPtr      Address of the block which is to be written back
              byteCnt       Size of the block to be written block.
              wait          Indicates if the call should block or not.

Return Value
None

Pre Condition
None

Post Condition
The dirty lines of the L2 Cache are being written back.

Writes
CGEM_L2WBAR_ADDR,CGEM_L2WWC_WC

Example

            Uint8* ptr_buffer;

            // Writeback the contents of the buffer.
            CACHE_wbL2(ptr_buffer, 100, CACHE_WAIT);

=============================================================================

CSL_IDEF_INLINE void CACHE_wbL2Wait | ( | void |  | ) |

============================================================================
CACHE_wbL2Wait

Description
This function is used to wait for the L2 writeback block operation to complete. This API should be used only if the CACHE_wbL2 was called with the CACHE_NOWAIT argument.

Arguments
None

Return Value
None

Pre Condition
CACHE_wbL2(wait=CACHE_NOWAIT) must be called.

Post Condition
The dirty lines of the L1D Block Cache have been written back.

Reads
CGEM_L2WWC_WC=0

Example

            CACHE_wbL2((void *)ptr_buffer, 128, CACHE_NOWAIT);
            ...
            CACHE_wbL2Wait();        // Wait for the writeback operation to complete.

=============================================================================

Copyright 2012, Texas Instruments Incorporated