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This structure holds the information required to initiate a iDMA Channel 0 Configuration(CFG) space Transfer request from the GEM. More...
#include <csl_idma.h>
Data Fields | |
Uint32 | mask |
IDMA channel 0 Mask. | |
Uint32 * | source |
IDMA channel 0 Source Address. | |
Uint32 * | destn |
IDMA channel 0 Destination Address. | |
Uint32 | count:4 |
Number of 32-word windows to be transfered. | |
Uint32 | intEnable:1 |
Boolean Flag to enable/disable CPU interrupt. |
This structure holds the information required to initiate a iDMA Channel 0 Configuration(CFG) space Transfer request from the GEM.
Uint32 CSL_IDMA_IDMA0CONFIG::count |
Number of 32-word windows to be transfered.
The count signifies the number of windows to be accessed during data transfer. Upto 16 contiguous 32-word regions can be specified using this field.
Uint32* CSL_IDMA_IDMA0CONFIG::destn |
IDMA channel 0 Destination Address.
The destination address must point to a 32-byte -aligned memory location local to GEM or to a valid configuration register space.
Boolean Flag to enable/disable CPU interrupt.
When this interrupt flag is set, a CPU Interrupt IDMA_INT0 is raised on completion of the block transfer/fill request.
Uint32 CSL_IDMA_IDMA0CONFIG::mask |
IDMA channel 0 Mask.
The mask allows unwanted registers within the window to be blocked from access, facilitating multiple read/write transactions to be completed with a single transfer command by the CPU. Each of the 32 bits of the mask correspond to a single register in the CFG space identified by the source/ destination address registers.
Uint32* CSL_IDMA_IDMA0CONFIG::source |
IDMA channel 0 Source Address.
The source address must point to a 32-byte-aligned memory location local to GEM or to a valid configuration register space.