# TSC

## Modules
| TSC Functions

## Detailed Description

## Introduction

### Overview

Time Stamp Counter is a free running 64-bit CPU counter that advances each CPU clock after counting is enabled. The counter is accessed using two 32-bit read-only control registers, Time Stamp Counter Registers – Low (TSCL) and Time Stamp Counter Registers – High (TSCH). The counter is enabled by writing to TSCL. The value written is ignored. Once enabled, counting cannot be disabled under program control. Counting is disabled in the following cases: a. After exiting the reset state. b. When the CPU is fully powered down.

### References

1. Joule CPU Architecture Spec

### Assumptions

The abbreviations TSC, tsc and Tsc have been used throughout this document to refer to C64+ Time Stamp Counter

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