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Specification of the Link Control 2 Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
uint8_t | deEmph |
[rw] Current De-emphasis level | |
uint8_t | pollDeemph |
[rw] De-emphasis level in polling-compliance state | |
uint8_t | cmplSos |
[rw] Compliance SOS. | |
uint8_t | entrModCompl |
[rw] Enter modified compliance. | |
uint8_t | txMargin |
[rw] Value of non-de-emphasized voltage level at transmitter pins. | |
uint8_t | selDeemph |
[rw] Selectable De-emphasis. | |
uint8_t | hwAutoSpeedDis |
[rw] Hardware Autonomous Speed Disable. | |
uint8_t | entrCompl |
[rw] Enter Compliance. | |
uint8_t | tgtSpeed |
[rw] Target Link Speed. |
Specification of the Link Control 2 Register.
This register may be used for both endpoint and root complex modes.
uint8_t pcieLinkCtrl2Reg_s::cmplSos |
[rw] Compliance SOS.
When this bit is set to 1, the LTSSM is required to send SKP Ordered Sets periodically in between the modified compliance patterns.
Field size: 1 bit
uint8_t pcieLinkCtrl2Reg_s::deEmph |
[rw] Current De-emphasis level
0 = -6 dB
1 = -3.5 dB
Field size: 1 bit
uint8_t pcieLinkCtrl2Reg_s::entrCompl |
[rw] Enter Compliance.
Software is permitted to force a Link to enter Compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1 in both components on a Link and then initiating a hot reset on the Link.
Field size: 1 bit
uint8_t pcieLinkCtrl2Reg_s::entrModCompl |
[rw] Enter modified compliance.
When this bit is set to 1, the device transmits Modified Compliance Pattern if the LTSSM enters Polling Compliance substate.
Field size: 1 bit
[rw] Hardware Autonomous Speed Disable.
0 = Enable hardware to change the link speed.
1 = Disables hardware from changing the Link speed for device specific reasons other than attempting to correct unreliable Link operation by reducing Link speed.
Field size: 1 bit
uint8_t pcieLinkCtrl2Reg_s::pollDeemph |
[rw] De-emphasis level in polling-compliance state
This bit sets the de-emphasis level in Polling Compliance state if the entry occurred due to the Enter Compliance bit being 1.
0 = -6 dB
1 = -3.5 dB
Field size: 1 bit
uint32_t pcieLinkCtrl2Reg_s::raw |
[ro] Raw image of register on read; actual value on write
uint8_t pcieLinkCtrl2Reg_s::selDeemph |
[rw] Selectable De-emphasis.
When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an upstream component. When the Link is operating at 2.5 GT/s speed, the setting of this bit has no effect.
0 = -6 dB
1 = -3.5 dB
Field size: 1 bit
uint8_t pcieLinkCtrl2Reg_s::tgtSpeed |
[rw] Target Link Speed.
1h = 2.5 GT/s Target Link Speed.
2h = 5.0 GT/s Target Link Speed.
Others = Reserved.
Field size: 4 bits
uint8_t pcieLinkCtrl2Reg_s::txMargin |
[rw] Value of non-de-emphasized voltage level at transmitter pins.
Field size: 3 bits