hyplnkLinkStatusReg_s Struct Reference
[HYPLNK LLD Register Definitions]

Specification of the Link Status Register. More...

#include <hyplnk.h>

Data Fields

uint32_t raw
 [ro] Raw image of register on read; actual value on write
uint8_t txPlsReq
 [ro] Number of lanes requested by PLS layer
uint8_t txPlsAck
 [ro] Number of lanes active by PLS layer
uint8_t txPmReq
 [ro] TX Power Management Sideband Control State
uint8_t txRSync
 [ro] Remote device has synced to the transmit traning sequence
uint8_t txPlsOK
 [ro] TX PLS layer is linked to the remote device
uint8_t txPhyEn
 [ro] Indicates which SERDES lanes are enabled
uint8_t txFlowSts
 [ro] Indicates which flow bit are set from the remote receiver.
uint8_t rxPlsReq
 [ro] Number of lanes requested by PLS for RX
uint8_t rxPlsAck
 [ro] Number of lanes active by PLS for RX
uint8_t rxPmReq
 [ro] RX Power Management Sideband Control State
uint8_t rxLSync
 [ro] Receive has synced to training sequence
uint8_t rxOneID
 [ro] Lane zero has been identified during training
uint8_t rxPhyEn
 [ro] Indicates which SERDES lanes are enabled

Detailed Description

Specification of the Link Status Register.

The Link status register is used to debug failed link conditions. It contains valuable information aoout the start of the link-state machines. It is used only to determine what might be causing the link failure. Because the source of this register can change quickly, this register updates only when a change has been detected and it is capable of transferring it to the bus clock domain.


Field Documentation

[ro] Receive has synced to training sequence

Field size: 1 bits

This is the source of the station management sync bit.

[ro] Lane zero has been identified during training

Field size: 1 bits

[ro] Indicates which SERDES lanes are enabled

Field size: 4 bits

[ro] Number of lanes active by PLS for RX

Field size: 2 bits

rxPlsAck# of lanes
00b 0
01b 1
10b 4
11b 4

[ro] Number of lanes requested by PLS for RX

Field size: 2 bits

rxPlsReq# of lanes
00b 0
01b 1
10b 4
11b NS

[ro] RX Power Management Sideband Control State

Field size: 2 bits

rxPmReq# of lanes
00b 0
01b 1
10b 4, transitioning to/from 0 lanes
11b 4

[ro] Indicates which flow bit are set from the remote receiver.

Only bits 0 and 1 are used.

Field size: 4 bits

[ro] Indicates which SERDES lanes are enabled

Field size: 4 bits

[ro] Number of lanes active by PLS layer

Field size: 2 bits

txPlsAck# of lanes
00b 0
01b 1
10b 4
11b 4

[ro] TX PLS layer is linked to the remote device

Field size: 1 bits

[ro] Number of lanes requested by PLS layer

Field size: 2 bits

txPlsReq# of lanes
00b 0
01b 1
10b 4
11b 4

[ro] TX Power Management Sideband Control State

Field size: 2 bits

txPmReq# of lanes
00b 0
01b 1
10b 4, transitioning to/from 0 lanes
11b 4

[ro] Remote device has synced to the transmit traning sequence

Field size: 1 bits

This is a latched version of the station management sync bit.


The documentation for this struct was generated from the following file:

Copyright 2012, Texas Instruments Incorporated