![]() |
![]() |
Specification of the Debug0 Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint8_t | tsLnkCtrl |
[ro] Link control bits advertised by link partner. | |
uint8_t | tsLaneK237 |
[ro] Currently receiving k237 (PAD) in place of lane number. | |
uint8_t | tsLinkK237 |
[ro] Currently receiving k237 (PAD) in place of link number. | |
uint8_t | rcvdIdle0 |
[ro] Receiver is receiving logical idle | |
uint8_t | rcvdIdle1 |
[ro] 2nd symbol is also idle | |
uint16_t | pipeTxData |
[ro] Pipe TX data | |
uint8_t | pipeTxDataK |
[ro] Pipe transmit K indication | |
uint8_t | skipTx |
[ro] A skip ordered set has been transmitted. | |
uint8_t | ltssmState |
[ro] LTSSM current state pcieLtssmState_e |
Specification of the Debug0 Register.
This register may be used for both endpoint and root complex modes.
uint8_t pcieDebug0Reg_s::ltssmState |
[ro] LTSSM current state pcieLtssmState_e
Field size: 5 bits
uint16_t pcieDebug0Reg_s::pipeTxData |
[ro] Pipe TX data
Field size: 16 bits
uint8_t pcieDebug0Reg_s::pipeTxDataK |
[ro] Pipe transmit K indication
Field size: 2 bits
uint8_t pcieDebug0Reg_s::rcvdIdle0 |
[ro] Receiver is receiving logical idle
Field size: 1 bit
uint8_t pcieDebug0Reg_s::rcvdIdle1 |
[ro] 2nd symbol is also idle
Field size: 1 bit
uint8_t pcieDebug0Reg_s::skipTx |
[ro] A skip ordered set has been transmitted.
Field size: 1 bit
uint8_t pcieDebug0Reg_s::tsLaneK237 |
[ro] Currently receiving k237 (PAD) in place of lane number.
Field size: 1 bit
uint8_t pcieDebug0Reg_s::tsLinkK237 |
[ro] Currently receiving k237 (PAD) in place of link number.
Field size: 1 bit
uint8_t pcieDebug0Reg_s::tsLnkCtrl |
[ro] Link control bits advertised by link partner.
Field size: 4 bits