pcieFltMask2Reg_s Struct Reference
[PCIE LLD Port Logic Register Definitions]

Specification of the Filter Mask 2 register. More...

#include <pcie.h>

Data Fields

uint32_t raw
uint8_t flushReq
 [rw] 1 = Enable the filter to handle flush request.
uint8_t dllpAbort
 [rw] 1 = Disable DLLP abort for unexpected CPL.
uint8_t vmsg1Drop
 [rw] 1 = Disable dropping of Vendor MSG Type 1.
uint8_t vmsg0Drop
 [rw] 1 = Disable dropping of Vendor MSG Type 0 with UR error reporting.

Detailed Description

Specification of the Filter Mask 2 register.

This register may be used for both endpoint and root complex modes.


Field Documentation

[rw] 1 = Disable DLLP abort for unexpected CPL.

Field size: 1 bit

[rw] 1 = Enable the filter to handle flush request.

Field size: 1 bit

[ro] Raw image of register on read; actual value on write

[rw] 1 = Disable dropping of Vendor MSG Type 0 with UR error reporting.

Field size: 1 bit

[rw] 1 = Disable dropping of Vendor MSG Type 1.

Field size: 1 bit


The documentation for this struct was generated from the following file:

Copyright 2012, Texas Instruments Incorporated