Packet Accelerator Low Level Driver

1.2.3.3

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Introduction

The packet accelerator sub-system (PASS) is designed to provide the input packet classification, checksum/CRC verification and generation, data manipulation and etc. The PASS consists of the following resources

The packet accelerator low level driver (PA LLD) provides configuration and control of the packet accelerator sub-system (PASS). The sub-system provides from network packet classification and routing based on network header information (see netlayers). The packet accelerator low level driver module (referred to as the module) provides APIs to configure the criteria used for from-network packet routing.

The module attempts to abstract the operation of the PASS from the application. The module uses the following rules when configuring the PASS:

With the exception of some initial setup functions, the module does not communicate directly with the sub-system. The output of the module is a formatted data block along with a destination address. The module user must send the formatted data to the sub-system. This is typically done by linking the created data block to a host packet descriptor, and then using the addressing information to send the created packet to the sub-system through the queue manager and PKTDMA.

For packets to the network, the sub-system provides ones complement checksum or CRC generation over a range provided by the module user. The range is not determined by sub-system by parsing the to-network packet, since it is assumed that the creator of the packet already has the start offset, length, initial checksum value and etc.

The low level driver maintains two tables of layer 2 and layer 3 configuration information. The memory for these tables is provided by the module user at run time. The module maintains ownership of these tables and the module user must not write to the memory once provided to the module.

In multi-core devices the module can be used in two different configurations. In independent core mode each core in a device has a unique set of tables. Although it is legal for any core to reference handles from other cores, this is not typically done. In this case cache coherency and cross core semaphores are not implemented by the module user. In common core mode there is only one set of tables and they are shared by all cores. Each core that uses the module must initialize it, but each core will provide the exact same buffers to the module. The module user will have the first core to initialize the module also initialize the table. Other cores will initialize their internal state but not initalize the table. In this mode cache coherency and cross core semaphores must be implemented by the module user to insure the integrity of the tables.


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