tsip_cfg.h File Reference

Telecom Serial Interface Port (TSIP) sub-system configuration for application. More...

#include <ti/csl/cslr_device.h>

Defines

#define TSIP_MAX_TIMESLOTS   128
#define TSIP_ELEMENT_BUF_SIZE   1
#define TSIP_N_PORTS   CSL_TSIP_PER_CNT
#define TSIP_SUB_FRAME_RATES   8, 8
#define TSIP_UNOPENED_PORT_FRAME_ALLOC   16
#define deviceWhoAmI()   DNUM
#define TSIP_ALIGN_STRUCT(x)   ((x) = (x+7)&(~7))
#define GLOBAL_ADDR(addr)   ((((uint32_t)addr>>24)&0xFF) ? ((uint32_t)addr) : ((1<<28)|((int16_t)DNUM<<24)|((uint32_t)(addr)&0x00ffffff)))
#define TSIP_FOR_LOOP_STAGGER_DELAY   7500
 When a channels DMA is disabled the super-frame interrupts stop as well. The delay puts some time between when the DMA is disabled and then re-enabled. If the value is too short then the disable-delay-enable has no effect. The amount of time required actually varies based on VBUS load. Smaller values (~100) work for the first couple of cores, but fail when more cores are downloaded. A value that is too long will also cause problems because the DMA will run past the current frame and the synchronization will start in the wrong buffer, causing the sync to retry indefinitely. A value of 7500 was found experimentally, but can be changed.
#define TSIP_STATIC_DMA_BUF
TSIP Port-Link-Timeslot Bit Allocation

Define which bits in a 16 bit timeslot field specify the port number, the link number, and the timeslot number. The bit allocation depends on the maximal number of ports, links, timeslots to be supported. In the following example, the maximal number of timeslots, link, and ports is 512, 8, 4, respectively.

15 14 13 12 11 9 8 0 /-------------------------------------------------------------\ | unused | port | link | timeslot | \-------------------------------------------------------------/

#define TSIP_PORT_MSB   13
#define TSIP_PORT_LSB   12
#define TSIP_LINK_MSB   11
#define TSIP_LINK_LSB   9
#define TSIP_TS_MSB   8
#define TSIP_TS_LSB   0

Detailed Description

Telecom Serial Interface Port (TSIP) sub-system configuration for application.

path ti/drv/tsip/tsip_cfg.h


Define Documentation

 
#define deviceWhoAmI (  )     DNUM

Macro to get the core ID

#define GLOBAL_ADDR ( addr   )     ((((uint32_t)addr>>24)&0xFF) ? ((uint32_t)addr) : ((1<<28)|((int16_t)DNUM<<24)|((uint32_t)(addr)&0x00ffffff)))

Macro to convert local address to global address

#define TSIP_ALIGN_STRUCT (  )     ((x) = (x+7)&(~7))

Macro to even align internal carving of memory

#define TSIP_ELEMENT_BUF_SIZE   1

The number of bytes allocated for each timeslot in the dma buffer. Set to 1 unless hardware companding is used

#define TSIP_FOR_LOOP_STAGGER_DELAY   7500

When a channels DMA is disabled the super-frame interrupts stop as well. The delay puts some time between when the DMA is disabled and then re-enabled. If the value is too short then the disable-delay-enable has no effect. The amount of time required actually varies based on VBUS load. Smaller values (~100) work for the first couple of cores, but fail when more cores are downloaded. A value that is too long will also cause problems because the DMA will run past the current frame and the synchronization will start in the wrong buffer, causing the sync to retry indefinitely. A value of 7500 was found experimentally, but can be changed.

This value is placed into a for loop during core synchronization:

volatile unsigned int x; for (x = 0; x < TSIP_FOR_LOOP_STAGGER_DELAY; x++);

#define TSIP_MAX_TIMESLOTS   128

The maximal number of TSIP timeslots to be used

#define TSIP_N_PORTS   CSL_TSIP_PER_CNT

Number of TSIP ports to be used

#define TSIP_STATIC_DMA_BUF

Define to use static bufffer allocation

#define TSIP_SUB_FRAME_RATES   8, 8

Sub frame size for each TSIP port

#define TSIP_UNOPENED_PORT_FRAME_ALLOC   16

Default number of frames per dma buffer for ports that haven't been enabled yet


Copyright 2012, Texas Instruments Incorporated