pciePlAckTimerReg_s Struct Reference
[PCIE LLD Port Logic Register Definitions]

Specification of the Ack Latency Time and Replay Timer register. More...

#include <pcie.h>

Data Fields

uint32_t raw
uint16_t rplyLmt
 [rw] Replay Time Limit.
uint16_t rndTrpLmt
 [rw] Round Trip Latency Time Limit.

Detailed Description

Specification of the Ack Latency Time and Replay Timer register.

This register may be used for both endpoint and root complex modes.


Field Documentation

[ro] Raw image of register on read; actual value on write

[rw] Round Trip Latency Time Limit.

The Ack/Nak latency timer expires when it reaches this limit. Write sticky, a reset will not clear this field

Field size: 16 bits

[rw] Replay Time Limit.

The replay timer expires when it reaches this limit. Write sticky, a reset will not clear this field

Field size: 16 bits


The documentation for this struct was generated from the following file:

Copyright 2012, Texas Instruments Incorporated