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Specification of the Device Capabilities Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
uint8_t | pwrLimitScale |
[rw] Captured Slot Power Limit Scale. For upstream ports (EP ports) only. | |
uint8_t | pwrLimitValue |
[rw] Captured Slow Power Limit Value. For upstream ports (EP ports) only. | |
uint8_t | errRpt |
[rw] Role-based Error Reporting. Writable from internal bus interface. | |
uint8_t | l1Latency |
[rw] Endpoint L1 Acceptable Latency. Must be 0 in RC mode. It is 3h for EP mode. | |
uint8_t | l0Latency |
[rw] Endpoint L0s Acceptable Latency. Must be 0 in RC mode. It is 4h for EP mode. | |
uint8_t | extTagFld |
[rw] Extended Tag Field Supported. Writable from internal interface | |
uint8_t | phantomFld |
[rw] Phantom Field Supported. Writable from internal bus interface. | |
uint8_t | maxPayldSz |
[rw] Maximum Payload size supported. Writable from internal bus interface. |
Specification of the Device Capabilities Register.
This register may be used for both endpoint and root complex modes.
uint8_t pcieDeviceCapReg_s::errRpt |
[rw] Role-based Error Reporting. Writable from internal bus interface.
Field size: 1 bit
uint8_t pcieDeviceCapReg_s::extTagFld |
[rw] Extended Tag Field Supported. Writable from internal interface
Field size: 1 bit
uint8_t pcieDeviceCapReg_s::l0Latency |
[rw] Endpoint L0s Acceptable Latency. Must be 0 in RC mode. It is 4h for EP mode.
Field size: 3 bits
uint8_t pcieDeviceCapReg_s::l1Latency |
[rw] Endpoint L1 Acceptable Latency. Must be 0 in RC mode. It is 3h for EP mode.
Field size: 3 bits
uint8_t pcieDeviceCapReg_s::maxPayldSz |
[rw] Maximum Payload size supported. Writable from internal bus interface.
Field size: 3 bits
uint8_t pcieDeviceCapReg_s::phantomFld |
[rw] Phantom Field Supported. Writable from internal bus interface.
Field size: 2 bits
[rw] Captured Slot Power Limit Scale. For upstream ports (EP ports) only.
Field size: 2 bits
[rw] Captured Slow Power Limit Value. For upstream ports (EP ports) only.
Field size: 8 bits
uint32_t pcieDeviceCapReg_s::raw |
[ro] Raw image of register on read; actual value on write