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Specification of the Reset Command Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint8_t | flush |
[ro] Bridge flush status | |
uint8_t | initRst |
[w1] Write 1 to initiate a downstream hot reset sequence on downstream. |
Specification of the Reset Command Register.
uint8_t pcieRstCmdReg_s::flush |
[ro] Bridge flush status
Used to ensure no pending transactions prior to issuing warm reset. 0 = No transaction is pending. 1 = There are transactions pending.
Field size: 1 bit
uint8_t pcieRstCmdReg_s::initRst |
[w1] Write 1 to initiate a downstream hot reset sequence on downstream.
Field size: 1 bit