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Specification of the Root Error Status register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
uint8_t | aerIntMsg |
[rw] AER Interrupt Message Number. | |
uint8_t | ferrRcv |
[rw] Fatal Error Messages Received. | |
uint8_t | nfErr |
[rw] Non-Fatal Error Messages Received. | |
uint8_t | uncorFatal |
[rw] First Uncorrectable Fatal Received. | |
uint8_t | multFnf |
[rw] Multiple Uncorrectable Error (ERR_FATAL/NONFATAL) Received. | |
uint8_t | errFnf |
[rw] Uncorrectable Error (ERR_FATAL/NONFATAL) Received. | |
uint8_t | multCor |
[rw] Multiple Correctable Error (ERR_COR) Received. | |
uint8_t | corrErr |
[rw] Correctable Error (ERR_COR) Received. |
Specification of the Root Error Status register.
This register may be used for both endpoint and root complex modes.
uint8_t pcieRootErrStReg_s::aerIntMsg |
[rw] AER Interrupt Message Number.
Field size: 5 bits
uint8_t pcieRootErrStReg_s::corrErr |
[rw] Correctable Error (ERR_COR) Received.
Write 1 to clear
Field size: 1 bit
uint8_t pcieRootErrStReg_s::errFnf |
[rw] Uncorrectable Error (ERR_FATAL/NONFATAL) Received.
Write 1 to clear
Field size: 1 bit
uint8_t pcieRootErrStReg_s::ferrRcv |
[rw] Fatal Error Messages Received.
Write 1 to clear
Field size: 1 bit
uint8_t pcieRootErrStReg_s::multCor |
[rw] Multiple Correctable Error (ERR_COR) Received.
Write 1 to clear
Field size: 1 bit
uint8_t pcieRootErrStReg_s::multFnf |
[rw] Multiple Uncorrectable Error (ERR_FATAL/NONFATAL) Received.
Write 1 to clear
Field size: 1 bit
uint8_t pcieRootErrStReg_s::nfErr |
[rw] Non-Fatal Error Messages Received.
Write 1 to clear
Field size: 1 bit
uint32_t pcieRootErrStReg_s::raw |
[ro] Raw image of register on read; actual value on write
uint8_t pcieRootErrStReg_s::uncorFatal |
[rw] First Uncorrectable Fatal Received.
Write 1 to clear
Field size: 1 bit