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Specification of the Latency Timer and Bus Number Register. More...
#include <pcie.h>
Data Fields | |
| uint32_t | raw |
| [ro] Raw image of register on read; actual value on write | |
| uint8_t | secLatTmr |
| [ro] Secondary Latency Timer (N/A for PCIe) | |
| uint8_t | subBusNum |
| [rw] Subordinate Bus Number. This is highest bus number on downstream interface. | |
| uint8_t | secBusNum |
| [rw] Secondary Bus Number. It is typically 1h for RC. | |
| uint8_t | priBusNum |
| [rw] Primary Bus Number. It is 0 for RC and nonzero for switch devices only. | |
Specification of the Latency Timer and Bus Number Register.
| uint8_t pcieType1BusNumReg_s::priBusNum |
[rw] Primary Bus Number. It is 0 for RC and nonzero for switch devices only.
Field size: 8 bits
| uint8_t pcieType1BusNumReg_s::secBusNum |
[rw] Secondary Bus Number. It is typically 1h for RC.
Field size: 8 bits
| uint8_t pcieType1BusNumReg_s::secLatTmr |
[ro] Secondary Latency Timer (N/A for PCIe)
Field size: 8 bits
| uint8_t pcieType1BusNumReg_s::subBusNum |
[rw] Subordinate Bus Number. This is highest bus number on downstream interface.
Field size: 8 bits