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Specification of the Status Command Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint8_t | parity |
[rw] parity | |
uint8_t | sysError |
[rw] sys error | |
uint8_t | mstAbort |
[rw] mst abort | |
uint8_t | tgtAbort |
[rw] tgt abort | |
uint8_t | sigTgtAbort |
[rw] sig tgt abort | |
uint8_t | parError |
[rw] par error | |
uint8_t | capList |
[ro] cap list | |
uint8_t | stat |
[rw] stat | |
uint8_t | dis |
[ro] dis | |
uint8_t | serrEn |
[rw] serr en | |
uint8_t | resp |
[rw] resp | |
uint8_t | busMs |
[rw] enables mastership of the bus | |
uint8_t | memSp |
[rw] enables device to respond to memory access | |
uint8_t | ioSp |
[rw] enables device to respond to IO access |
Specification of the Status Command Register.
uint8_t pcieStatusCmdReg_s::busMs |
[rw] enables mastership of the bus
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::capList |
[ro] cap list
For PCIe, this field must be set to 1.
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::dis |
[ro] dis
Setting this bit disables generation of INTx messages.
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::ioSp |
[rw] enables device to respond to IO access
This functionality is not supported in PCIESS and therefore this bit is set to 0.
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::memSp |
[rw] enables device to respond to memory access
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::mstAbort |
[rw] mst abort
Set when a requester receives a completion with unsupported request completion status
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::parError |
[rw] par error
This bit is set by a requester if the parError bit is set in its Command register and either the condition that the requester receives a poisoned completion or the condition that the requester poisons a write request is true.
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::parity |
[rw] parity
Set if received a poisoned TLP
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::resp |
[rw] resp
This bit controls whether or not the device responds to detected parity errors (poisoned TLP). This error is typically reported as an unsupported request and may also result in a non-fatal error message if serrEn = 1. If this bit is set, the PCIESS will respond normally to parity errors. If this bit is cleared, the PCIESS will ignore detected parity errors.
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::serrEn |
[rw] serr en
When set, it enables generation of the appropriate PCI Express error messages to the Root Complex.
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::sigTgtAbort |
[rw] sig tgt abort
Set when a function acting as a completer terminates a request by issuing completer abort completion status to the requester.
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::stat |
[rw] stat
Indicates that the function has received an interrupt.
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::sysError |
[rw] sys error
Set if function sends an ERR_FATAL or ERR_NONFATAL message and serrEn bit is set
Field size: 1 bit
uint8_t pcieStatusCmdReg_s::tgtAbort |
[rw] tgt abort
Set when a requester receives a completion with completer abort status.
Field size: 1 bit