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Specification of the Outbound Translation Region Offset Low and Index Register. More...
#include <pcie.h>
Data Fields | |
| uint32_t | raw |
| [ro] Raw image of register on read; actual value on write | |
| uint16_t | offsetLo |
| [rw] Offset bits for the translation region | |
| uint8_t | enable |
| [rw] Enable translation region | |
Specification of the Outbound Translation Region Offset Low and Index Register.
There is one register per translation region (0-7)
| uint8_t pcieObOffsetLoReg_s::enable |
[rw] Enable translation region
Field size: 1 bit
| uint16_t pcieObOffsetLoReg_s::offsetLo |
[rw] Offset bits for the translation region
Field size: 12 bits