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Specification of the SerDes Control And Status 4 Register. More...
#include <hyplnk.h>
Data Fields | |
| uint32_t | raw |
| [ro] Raw image of register on read; actual value on write | |
| uint16_t | s4Ctl |
| [rw] Unused | |
| uint8_t | dvQuick |
| [rw] For testing purposes | |
Specification of the SerDes Control And Status 4 Register.
The SerDes Control and Status Register is used to quicken DV so that the periodic wake-up timer can be tested more easily and to allow change to the SerDes non-runtime power levels. The power-level controls were added to reduce SerDes sleep mode functionality risk. It provides the ability to enable or disable sleep functionality for both the transmit and receive SerDes lanes.
[rw] For testing purposes
DVQUICK reduces the periodic wake up event prescaler to 256 clocks instead of 65,536 clocks. It allow for more exhaustive testing of the PWC.
| uint16_t hyplnkSERDESControl4Reg_s::s4Ctl |
[rw] Unused
Field size: 11 bits