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Specification of the Port Link Control Register. More...
#include <pcie.h>
Data Fields | |
| uint32_t | raw |
| [ro] Raw image of register on read; actual value on write | |
| uint8_t | lnkMode |
| [rw] Link Mode | |
| uint8_t | lnkRate |
| [rw] Link Rate | |
| uint8_t | fLnkMode |
| [rw] Fast link mode | |
| uint8_t | dllEn |
| [rw] DLL link enable | |
| uint8_t | rstAsrt |
| [rw] Reset Assert | |
| uint8_t | lpbkEn |
| [rw] Loopback Enable | |
| uint8_t | scrmDis |
| [rw] Scramble Disable | |
| uint8_t | msgReq |
| [rw] Other Message Request | |
Specification of the Port Link Control Register.
This register may be used for both endpoint and root complex modes.
| uint8_t pcieLnkCtrlReg_s::dllEn |
[rw] DLL link enable
DLL Link Enable. Enable link initialization.
Field size: 1 bit
| uint8_t pcieLnkCtrlReg_s::fLnkMode |
[rw] Fast link mode
Set all internal timers to fast mode for simulation purposes.
Field size: 1 bit
| uint8_t pcieLnkCtrlReg_s::lnkMode |
[rw] Link Mode
| lnkMode | # of lanes |
|---|---|
| 0x1 | 1 |
| 0x3 | 2 |
| 0x7 | 4 |
| 0xf | 8 |
| 0x1f | 16 |
| 0x3f | 32 |
| others | reserved |
Field size: 6 bits
| uint8_t pcieLnkCtrlReg_s::lnkRate |
[rw] Link Rate
For 2.5 GT/s it is 0x1. This register does not affect any functionality.
Field size: 4 bits
| uint8_t pcieLnkCtrlReg_s::lpbkEn |
[rw] Loopback Enable
Field size: 1 bit
| uint8_t pcieLnkCtrlReg_s::msgReq |
[rw] Other Message Request
Set to transmit the message contained in pciePlOMsgReg_s
Field size: 1 bit
| uint8_t pcieLnkCtrlReg_s::rstAsrt |
[rw] Reset Assert
Triggers a recovery and forces the LTSSM to the Hot Reset state. Downstream ports (RC ports) only.
Field size: 1 bit
| uint8_t pcieLnkCtrlReg_s::scrmDis |
[rw] Scramble Disable
Field size: 1 bit