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| pcieAccrReg_s | Specification of the Advanced capabilities and control Register |
| pcieAckFreqReg_s | Specification of the Ack Frequency register |
| pcieActStatusReg_s | Specification of the Activity Status Register |
| pcieBar32bitReg_s | Specification of the Base Address Register (BAR) |
| pcieBarCfg_s | Specification of pcieBarCfg |
| pcieBarReg_s | Specification of the Base Address Register (BAR) |
| pcieBistReg_s | Specification of the BIST Header Register |
| pcieCapPtrReg_s | Specification of the Capability Pointer Register |
| pcieCfgTransReg_s | Specification of the Configuration Transaction Setup Register |
| pcieCmdStatusReg_s | Specification of the Command Status Register |
| pcieCorErrMaskReg_s | Specification of the Correctable Error Mask register |
| pcieCorErrReg_s | Specification of the Correctable Error Status register |
| pcieDebug0Reg_s | Specification of the Debug0 Register |
| pcieDebug1Reg_s | Specification of the Debug 1 Register |
| pcieDevCap2Reg_s | Specification of the Device Capabilities 2 Register |
| pcieDeviceCapReg_s | Specification of the Device Capabilities Register |
| pcieDevStatCtrl2Reg_s | Specification of the Device Status and Control Register 2 |
| pcieDevStatCtrlReg_s | Specification of the Device Status and Control Register |
| pcieDiagCtrlReg_s | Specification of the Diagnostic Control register |
| pcieEndianReg_s | Specification of the Endian Register |
| pcieEpIrqClrReg_s | Specification of the Endpoint Interrupt Request Clear Register |
| pcieEpIrqSetReg_s | Specification of the Endpoint Interrupt Request Set Register |
| pcieEpIrqStatusReg_s | Specification of the Endpoint Interrupt status Register |
| pcieErrIrqEnableClrReg_s | Specification of the ERR Interrupt Enable Clear Register |
| pcieErrIrqEnableSetReg_s | Specification of the ERR Interrupt Enable Set Register |
| pcieErrIrqStatusRawReg_s | Specification of the Raw ERR Interrupt Status Register |
| pcieErrIrqStatusReg_s | Specification of the ERR Interrupt Enabled Status Register |
| pcieErrSrcIDReg_s | Specification of the Error Source Identification register |
| pcieExpRomReg_s | Specification of the Expansion ROM Register |
| pcieExtCapReg_s | Specification of the Extended Capabilities Header register |
| pcieFltMask2Reg_s | Specification of the Filter Mask 2 register |
| pcieGen2Reg_s | Specification of the Gen2 Register |
| pcieGenPurposeReg_s | Specification of a General Purpose register |
| pcieHdrLogReg_s | Specification of the Header Log registers |
| pcieIbBarReg_s | Specification of the Inbound Translation BAR Match Register |
| pcieIbOffsetReg_s | Specification of the Inbound Translation Address Offset Register |
| pcieIbStartHiReg_s | Specification of the Inbound Translation Start Address High Register |
| pcieIbStartLoReg_s | Specification of the Inbound Translation Start Address Low Register |
| pcieIbTransCfg_s | Specification of pcieIbTransCfg |
| pcieIntPinReg_s | Specification of the Interrupt Pin Register |
| pcieIoBaseReg_s | Specification of the IO TLP Base Register |
| pcieIrqEOIReg_s | Specification of the End of Interrupt Register |
| pcieLaneSkewReg_s | Specification of the Lane Skew register |
| pcieLegacyIrqEnableClrReg_s | Specification of the Legacy Interrupt Enable Clear Register |
| pcieLegacyIrqEnableSetReg_s | Specification of the Legacy Interrupt Enable Set Register |
| pcieLegacyIrqStatusRawReg_s | Specification of the Legacy Raw Interrupt Status Register |
| pcieLegacyIrqStatusReg_s | Specification of the Legacy Interrupt Enabled Status Register |
| pcieLinkCapReg_s | Specification of the Link Capabilities Register |
| pcieLinkCtrl2Reg_s | Specification of the Link Control 2 Register |
| pcieLinkStatCtrlReg_s | Specification of the Link Status and Control Register |
| pcieLnkCtrlReg_s | Specification of the Port Link Control Register |
| pcieMsiCapReg_s | Specification of the MSI capabilities Register |
| pcieMsiDataReg_s | Specification of the MSI Data Register |
| pcieMsiIrqEnableClrReg_s | Specification of the MSI Interrupt Enable Clear Register |
| pcieMsiIrqEnableSetReg_s | Specification of the MSI Interrupt Enable Set Register |
| pcieMsiIrqReg_s | Specification of the MSI Interrupt IRQ Register |
| pcieMsiIrqStatusRawReg_s | Specification of the MSI Raw Interrupt Status Register Register |
| pcieMsiIrqStatusReg_s | Specification of the MSI Interrupt Enabled Status Register Register |
| pcieMsiLo32Reg_s | Specification of the MSI lower 32 bits Register |
| pcieMsiUp32Reg_s | Specification of the MSI upper 32 bits Register |
| pcieObOffsetHiReg_s | Specification of the Outbound Translation Region Offset High Register |
| pcieObOffsetLoReg_s | Specification of the Outbound Translation Region Offset Low and Index Register |
| pcieObSizeReg_s | Specification of the Outbound Size Register |
| pciePciesCapReg_s | Specification of the PCI Express Capabilities Register |
| pciePcsCfg0Reg_s | Specification of the PCS Configuration 0 Register |
| pciePcsCfg1Reg_s | Specification of the PCS Configuration 1 Register |
| pciePcsStatusReg_s | Specification of the PCS Status Register |
| pciePidReg_s | Specification of the PCIe Peripheral ID Register |
| pciePlAckTimerReg_s | Specification of the Ack Latency Time and Replay Timer register |
| pciePlForceLinkReg_s | Specification of the Port Force Link register |
| pciePlOMsgReg_s | Specification of the Other Message register |
| pciePMCapCtlStatReg_s | Specification of the Power Management Capabilities Control and Status Register |
| pciePMCapReg_s | Specification of the Power Management Capability Register |
| pciePmCfgReg_s | Specification of the Power Management Configuration Register |
| pciePmCmdReg_s | Specification of the Power Management Command Register |
| pciePmRstIrqEnableClrReg_s | Specification of the Power Management and Reset Interrupt Enable Clear Register |
| pciePmRstIrqEnableSetReg_s | Specification of the Power Management and Reset Interrupt Enable Set Register |
| pciePmRstIrqStatusRawReg_s | Specification of the Raw Power Management and Reset Interrupt Status Register |
| pciePmRstIrqStatusReg_s | Specification of the Power Management and Reset Interrupt Enabled Status Register |
| pciePrefBaseUpperReg_s | Specification of the Prefetchable Memory Base Upper Register |
| pciePrefLimitUpperReg_s | Specification of the Prefetchable Memory Limit Upper Register |
| pciePrefMemReg_s | Specification of the Prefetchable Memory Limit and Base Register |
| pciePriorityReg_s | Specification of the Transaction Priority Register |
| pcieRegisters_s | Specification all registers |
| pcieRevIdReg_s | Specification of the Class code and revision ID Register |
| pcieRootCtrlCapReg_s | Specification of the Root Control and Capabilities Register |
| pcieRootErrCmdReg_s | Specification of the Root Error Command register |
| pcieRootErrStReg_s | Specification of the Root Error Status register |
| pcieRootStatusReg_s | Specification of the Root Status and Control register |
| pcieRstCmdReg_s | Specification of the Reset Command Register |
| pcieSerdesCfg0Reg_s | Specification of the SERDES config 0 Register |
| pcieSerdesCfg1Reg_s | Specification of the SERDES config 1 Register |
| pcieSlotCapReg_s | Specification of the Slot Capabilities register |
| pcieSlotStatCtrlReg_s | Specification of the Slot Status and Control register |
| pcieStatusCmdReg_s | Specification of the Status Command Register |
| pcieSubIdReg_s | Specification of the Subsystem Vendor ID Register |
| pcieSymNumReg_s | Specification of the Symbol Number register |
| pcieSymTimerFltMaskReg_s | Specification of the Symbol Timer and Filter Mask register |
| pcieTlpCfgReg_s | Specification of the TLP configuration Register |
| pcieType0Bar32bitIdx_s | pcieBar32bitReg_s register plus an index (End Point BAR) |
| pcieType0BarIdx_s | pcieBarReg_s register plus an index (End Point BAR) |
| pcieType1Bar32bitIdx_s | pcieBar32bitReg_s register plus an index (Root Complex BAR) |
| pcieType1BarIdx_s | pcieBarReg_s register plus an index (Root Complex BAR) |
| pcieType1BistHeaderReg_s | Specification of the BIST, Header Type, Latency Time and Cache Line Size Regiser |
| pcieType1BridgeIntReg_s | Specification of the Bridge Control and Interrupt Register |
| pcieType1BusNumReg_s | Specification of the Latency Timer and Bus Number Register |
| pcieType1CapPtrReg_s | Specification of the Capabilities Pointer Register |
| pcieType1ExpnsnRomReg_s | Specification of the Expansion ROM Base Address Register |
| pcieType1IOSpaceReg_s | Specification of the IO Base and Limit Upper 16 bits Register |
| pcieType1MemspaceReg_s | Specification of the Memory Limit and Base Register |
| pcieType1SecStatReg_s | Specification of the Secondary Status and IO Base/Limit Register |
| pcieUncErrMaskReg_s | Specification of the Uncorrectable Error Mask register |
| pcieUncErrReg_s | Specification of the Uncorrectable Error Status register |
| pcieUncErrSvrtyReg_s | Specification of the Uncorrectable Error Severity register |
| pcieVndDevIdReg_s | Specification of the Vendor Device ID Register |