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Specification of the MSI capabilities Register. More...
#include <pcie.h>
Data Fields | |
| uint32_t | raw |
| [ro] Raw image of register on read; actual value on write | |
| uint8_t | en64bit |
| [rw] 64bit addressing enabled | |
| uint8_t | multMsgEn |
| [rw] Multiple Msg enabled | |
| uint8_t | multMsgCap |
| [rw] Multipe Msg capable | |
| uint8_t | msiEn |
| [rw] MSI enabled | |
| uint8_t | nextCap |
| [rw] Next capability pointer | |
| uint8_t | capId |
| [ro] MSI capability ID | |
Specification of the MSI capabilities Register.
This register may be used for both endpoint and root complex modes.
| uint8_t pcieMsiCapReg_s::capId |
[ro] MSI capability ID
Field size: 8 bits
| uint8_t pcieMsiCapReg_s::en64bit |
[rw] 64bit addressing enabled
Field size: 1 bit
| uint8_t pcieMsiCapReg_s::msiEn |
[rw] MSI enabled
MSI Enabled. When set, INTx must be disabled.
Field size: 1 bit
| uint8_t pcieMsiCapReg_s::multMsgCap |
[rw] Multipe Msg capable
Multiple message capable.
| multMsgCap | Number of messages |
|---|---|
| 0 | 1 |
| 1 | 2 |
| 2 | 4 |
| 3 | 8 |
| 4 | 16 |
| 5 | 32 |
| others | reserved |
Field size: 3 bits
| uint8_t pcieMsiCapReg_s::multMsgEn |
[rw] Multiple Msg enabled
Indicates that multiple message mode is enabled by software. Number of messages enabled must not be greater than multMsgCap
| multMsgEn | Number of messages |
|---|---|
| 0 | 1 |
| 1 | 2 |
| 2 | 4 |
| 3 | 8 |
| 4 | 16 |
| 5 | 32 |
| others | reserved |
Field size: 3 bits
| uint8_t pcieMsiCapReg_s::nextCap |
[rw] Next capability pointer
By default, it points to PCI Express Capabilities structure.
Field size: 8 bits